Datasheet

LT3495/LT3495B/
LT3495-1/LT3495B-1
7
3495b1b1fa
BLOCK DIAGRAM
PIN FUNCTIONS
GND (Pins 1, 2): Ground. Tie directly to local ground
plane.
V
CC
(Pin 3): Input Supply Pin. Must be locally by-
passed.
CTRL (Pin 4): Dimming Pin. If not used, tie CTRL to 1.5V
or higher. If in use, drive CTRL below 1.235V to override
the internal reference. See Applications section for more
information.
SHDN (Pin 5): Shutdown Pin. Tie to 1.5V or more to en-
able chip. Ground to shut down.
FB (Pin 6): Feedback Pin. Minimize the metal trace area
to this pin to minimize noise. Reference voltage is 1.235V.
There is an internal 76k resistor from the FB pin to GND. To
achieve the desired output voltage, choose R1 according
to the following formula:
 R1=76•(V
OUT
/1.235 – 1)kΩ
V
OUT
(Pin 7): Drain of Output Disconnect PMOS. Place a
bypass capacitor from this pin to GND. See Applications
information.
CAP (Pins 8, 9): Source of Output Disconnect PMOS.
Place a bypass capacitor from this pin to GND.
SW (Pin 10): Switch Pin. This is the collector of the in-
ternal NPN power switch. Minimize the metal trace area
connected to this pin to minimize EMI.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to PCB.
10
+
–
+
+
6
3
4
FB
CTRL
76k
5
SHDN
V
REF
SWITCH CONTROL
SHUNT CONTROL
DISCONNECT
CONTROL
START-UP CONTROL
V
CC
INPUT
SW
2
GND
1 11
GND
8
CAP
9
CAP
7
V
OUT
R1
3495 BD