Datasheet

LT3489
4
3489f
PI FU CTIO S
UUU
BLOCK DIAGRA
W
V
C
(Pin 1): Error Amplifi er Output Pin. Tie external compen-
sation network to this pin, or use the internal compensation
network by shorting the V
C
pin to the COMP pin.
FB (Pin 2): Feedback Pin. Reference voltage is 1.235V.
Connect resistive divider tap here. Minimize the trace area at
FB. Set V
OUT
according to V
OUT
= 1.235 • (1 + R1/R2).
SHDN (Pin 3): Shutdown Pin. Tie to 2V or more to enable
device. Ground to shut down. Do not fl oat this pin.
GND (Pin 4): Ground. Tie directly to local ground plane.
SW (Pin 5): Switch Pin. This is the collector of the internal
NPN power switch. Minimize the metal trace area connected
to this pin to minimize EMI.
V
IN
(Pin 6): Input Supply Pin. Must be locally bypassed.
COMP (Pin 7): Internal Compensation Pin. Provides an
internal compensation network. Tie directly to the V
C
pin
for internal compensation. Tie to GND if not in use.
SS (Pin 8): Soft-Start Pin. Place a soft-start capacitor here.
Upon start-up, 10μA of current charges the capacitor to
1.8V. Use a larger capacitor for slower start-up. Leave
fl oating if not in use.
Exposed Pad (Pin 9): Ground. Must be soldered to
PCB.
Σ
–
+
–
+
A2
FB
SHDN
SHUTDOWN
V
IN
DRIVER
Q1
0.01Ω
100k
125pF
SW
GND
COMPARATOR
5
V
C
1
COMP
4
S
RQ
RAMP
GENERATOR
2MHz
OSCILLATOR
–
+
23
1.235V
REFERENCE
6
SS
+
8
7
R1 (EXTERNAL)
FB
V
OUT
R2 (EXTERNAL)
A1
GND
9
3489 F01
Figure 1. Block Diagram