Datasheet

LT3487
13
3487f
TYPICAL APPLICATIO
U
V
POS
Load Step Response V
NEG
Load Step Response
+15V and –8V Boost and Inverting CCD Bias
SWN
L2
15µH
L1
10µH
V
IN
CAP
R1
549k
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
L3
15µH
R2 324k
C7 47pF
FBN
RUN/SSRUN/SS
V
NEG
–8V
90mA
C6
100nF
C4
4.7µF
3487 TA02a
C5
100nF
V
POS
15V
45mA
C1
1µF
C2
2.2µF
C3
22µF
V
IN
3V TO 12V
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
V
POS
100mV/DIV
AC-COUPLED
45mA
I
POS
15mA
100µs/DIV
3487 TA02b
V
IN
= 3.6V
V
NEG
20mV/DIV
AC-COUPLED
–50mA
I
NEG
–90mA
100µs/DIV
3487 TA02c
V
IN
= 3.6V
The positive channel’s response is stable, but slightly
underdamped. A phase lead capacitor (C8) can be added
to provide more ideal phase margin.
V
POS
Load Step Response (with Phase Lead Capacitor)
V
POS
100mV/DIV
AC-COUPLED
45mA
I
POS
15mA
100µs/DIV
3487 TA02d
V
IN
= 3.6V
CAP
R2
549k
C8
10pF
FBP
3487 TA02e