Datasheet

10
LT3473/LT3473A
3473f
between the OUT pin and ground. A ceramic capacitor with
a value of 1µF is a good choice. The voltage drop (PNP
V
CESAT
) can be accounted for by setting the output voltage
according to the following formula:
VVV V
R
R
V
OUT INT CESAT REF CESAT
==+
⎛
⎝
⎜
⎞
⎠
⎟
–•–1
2
1
Auxiliary NPN Devices (LT3473A Only)
The LT3473A has two auxiliary NPNs as shown in the
Block Diagram that can provide intermediate outputs less
than OUT. The collectors of the NPNs are connected to the
OUT pin internally. Each NPN can dissipate 100mW safely
and has a minimum beta of 60. A resistor string can be
APPLICATIO S I FOR ATIO
WUUU
2
4
R
EXT1
R
EXT2
R
EXT3
NE1
3
NB1
OUT
6
NE2
5
NB2
3473 F05
Figure 5. Auxiliary NPN Transistors in LT3473A. R
EXT1
, R
EXT2
and R
EXT3
Set Intermediate Voltage at NE1 and NE2
connected to the two bases as shown in Figure 5 to
generate buffered voltage at the emitters. When sourcing
high current at low voltage, keep in mind that the NPNs
will be dissipating a fair amount of power, which must be
supplied by the DC/DC converter.
Thermal Shutdown
The LT3473 has thermal shutdown circuitry that shuts down
the part when the junction temperature reaches approxi-
mately 145°C to protect the part from abnormal operation
with high power dissipation, such as an output short cir-
cuit or excessive power dissipation in the auxiliary NPNs.
The part will turn back on when the junction cools down to
approximately 125°C. If the abnormal condition remains,
the part will turn on and off while maintaining the junction
temperature within the window between 125°C and 145°C.
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
pin has sharp rise and fall edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. Recommended component place-
ment is shown in Figure 6.
Figure 6. Recommended Component Placement
OUT
1
2
3
4
13
5
6
12
11
10
9
8
7
3473 F06a
OUT
1
2
3
4
9
8
7
6
5
3473 F06b