Datasheet

17
LT3437
3437fc
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3437 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3437 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. In addition, V
IN
and BIAS quiescent
currents are reduced to typically 45µA and 110µA, respec-
tively, during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT3437 operates in sleep mode increases and the
average input current is greatly reduced, resulting in
higher efficiency.
The minimum average input current depends on the V
IN
to
V
OUT
ratio, V
C
frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
III
V
V
III
IN AVG VINS
SHDN
OUT
IN
BIASS FB S
()
≅ ++
⎛
⎝
⎜
⎞
⎠
⎟
++
()
()
η
where
I
VINS
= input pin current in sleep mode
V
OUT
= output voltage
V
IN
= input voltage
I
BIASS
= BIAS pin current in sleep mode
I
FB
= feedback network current
I
S
= catch diode reverse leakage at V
OUT
η = low current efficiency (non Burst Mode operation)
Example: For V
OUT
= 3.3V, V
IN
= 12V
IAA
AA
IN AVG()
.
.
≅ µ+µ+
⎛
⎝
⎜
⎞
⎠
⎟
µ+ µ+
45 5
33
12
110 12 5 0
..
.
5
08
45 5 42 92
µ
()
()
=µ+µ+µ=µ
A
AA A A
During the sleep portion of the Burst Mode cycle, the V
C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
If Burst Mode operation is undesirable, it can be defeated
by placing 2V or greater on the SYNC pin. When Burst
Mode operation is defeated, output ripple at light loads will
be reduced at the expense of light load efficiency.
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
the switch duty cycle. At high input to output voltage
ratios, the diode conducts most of the time. As the ratio
approaches unity, the diode conducts only a small fraction
of the time. The most stressful condition for the diode is
when the output is short circuited. Under this condition,
the diode must safely handle I
PEAK
at maximum duty cycle.
To maximize high and low load current efficiency, a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT3437 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
Figure 5. I
Q
vs V
IN
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
40
100
10 20 30 40
3435 F05
50
200
20
60
80
120
140
160
180
8060 70
V
OUT
= 3.3V
APPLICATIO S I FOR ATIO
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