Datasheet

LT3435
19
3435fa
Figure 9. Power Good
Figure 10. Power Good Circuits
APPLICATIO S I FOR ATIO
WUUU
V
IN
PG
PGFB
LT3435
PG at 80% V
OUT
with 100ms Delay
0.27µF
C
OUT
C
OUT
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT3435
V
OUT
Disconnect at 80% V
OUT
with 100ms Delay
0.27µF
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT3435
PG at V
IN
> 4V with 100ms Delay
0.27µF
V
OUT
= 3.3V
200k
511k
200k
100k
165k
FB
C
T
V
IN
PG
PGFB
LT3435
V
OUT
Disconnect 3.3V Logic Signal
with 100µs Delay
270pF
200k
V
OUT
= 12V
3435 F10
866k
100k
FB
C
T
C
OUT
C
OUT
threshold during normal operation, the C
T
pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
T
= 0.1µF. The PGOOD pin has
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT3435 Power Good circuitry. Figure 10
shows several different configurations for the LT3435
Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
V
OUT
500mV/DIV
V
SHDN
2V/DIV
TIME (10ms/DIV)
3435 F09
PG
100k TO V
IN
V
CT
500mV/DIV