Datasheet

LT3435
18
3435fa
Example:
R
A
M
R
M
M
A
M
k
1
12 2
155
13
3
513
1
65
1
13
649
408
=
µ
()
= Ω
=
Ω
()
= ΩΩ
Ω
µ
Ω
=
–
.
.
.
.
––
.
.
(Nearest 1% 6.49M )
R2 =
1.3
7 – 1.3
1.3M
(Nearest 1% 412k)
See the Typical Performance Characteristics section for
graphs of SHDN and V
IN
currents verses input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between
5% and 75% to the LT3435 SYNC pin.
The synchronizing range is equal to initial operating
frequency up to
700kHz . This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency ( 575kHz ), not the typical oper-
ating frequency of
300kHz . Caution should be used when
synchronizing above
575kHz because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
Figure 8. Undervoltage Lockout
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid and
hazardous conditions for the SW pin.
If the synchronization signal is present during Burst Mode
operation, synchronization will occur during the burst
portion of the output waveform. Synchronizing the LT3435
during Burst Mode operation may alter the natural burst
frequency which can lead to jitter and increased ripple in
the burst waveform.
If no synchronization is required this pin should be con-
nected to ground.
POWER GOOD
The LT3435 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
the PGFB pin drops below V
PGFB
the C
T
pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
T
pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
current is sourced
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
APPLICATIO S I FOR ATIO
WUUU
ENABLE
1.3V
3435 F08
3µA
SHDN
R2
2.4V
–
+
SHDN
COMP
–
+
V
IN
COMP
15
V
IN
V
OUT
LT3435
4
R1
R3