Datasheet

LT3434
15
3434fb
C
CSS
= 1000pF
C
CSS
= 0.01µF
C
CSS
= 0.1µF
APPLICATIO S I FOR ATIO
WUUU
limits the switch current via the V
C
pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C
SS
pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the C
SS
capacitor
exceeds the C
SS
threshold (I
CSS
), the voltage ramp of the
output capacitor is limited by reducing the V
C
pin voltage.
The C
SS
threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
dV
dt
I
C
CSS
SS
=
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
average input current is greatly reduced resulting in higher
efficiency.
The minimum average input current depends on the V
IN
to
V
OUT
ratio, V
C
frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
III
V
V
III
IN AVG VINS SHDN
OUT
IN
BIASS FB S
()
≅ ++
⎛
⎝
⎜
⎞
⎠
⎟
++
()
()
η
where
I
VINS
= input pin current in sleep mode
V
OUT
= output voltage
V
IN
= input voltage
I
BIASS
= BIAS pin current in sleep mode
I
FB
= feedback network current
I
S
= catch diode reverse leakage at V
OUT
η = low current efficiency (non Burst Mode operation)
Example: For V
OUT
= 3.3V, V
IN
= 12V
IAA
AAA
AA A A
IN AVG()
.
..
.
=µ+µ+
⎛
⎝
⎜
⎞
⎠
⎟
µ+ µ+ µ
()
()
=µ+µ+µ=µ
45 5
33
12
125 12 5 0 5
085
45 5 44 99
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3434 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3434 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. In addition, V
IN
and BIAS quiescent
currents are reduced to typically 45µA and 110µA respec-
tively during the sleep time. As the load current increases
towards a no load condition, the percentage of time that
the LT3434 operates in sleep mode increases and the
Figure 5. I
Q
vs V
IN
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
50
100
10
20
30 40
3434 F05
50
150
25
75
125
60
V
OUT
= 3.3V
During the sleep portion of the Burst Mode cycle, the V
C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
Figure 4. V
OUT
dV/dt
V
OUT
0.5V/DIV
V
IN
= 12V 1ms/DIV 3434 F04
V
OUT
= 3.3V
I
LOAD
= 500mA