Datasheet

23
LT3431
sn3431 3431fs
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, C
SS
and Q1.
As the output starts to rise, Q1 turns on, regulating switch
current via the V
C
pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through C
SS
defined by R4 and Q1’s V
BE
. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
Rise Time
RC V
V
SS OUT
BE
=
()( )( )
4
Using the values shown in Figure 10,
Rise Time ms=
()( )
()
=
47 10 15 10 5
07
5
39
••
.
–
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
APPLICATIO S I FOR ATIO
WUUU
Dual Polarity Output Converter
The circuit in Figure 14a generates both positive and
negative 5V outputs with all components under 3mm
height. The topology for the 5V output is a standard buck
converter. The –5V output uses a second inductor L2,
diode D3, and output capacitor C6. The capacitor C4
couples energy to L2 and ensures equal voltages across
L2 and L1 during steady state. Instead of using a trans-
former for L1 and L2, uncoupled inductors were used
because they require less height than a single transformer,
can be placed separately in the circuit layout for optimized
space savings and reduce overall cost. This is true even
when the uncoupled inductors are sized (twice the value of
inductance of the transformer) in order to keep ripple
current comparable to the transformer solution. If a single
transformer becomes available to provide a better height
/cost solution, refer to the Dual Output SEPIC circuit
description in Design Note 100 for correct transformer
connection.
During switch on-time, in steady state, the voltage across
both L1 and L2 is positive and equal ; with energy (and
current) ramping up in each inductor. The current in L2 is
provided by the coupling capacitor C4. During switch off-
time, current ramps downward in each inductor. The
current in L2 and C4 flows via the catch diode D3, charging
the negative output capacitor C6. If the negative output is
not loaded enough it can go severely unregulated (become
more negative). Figure 14b shows the maximum allow-
able –5V output load current (vs load current on the 5V
output) that will maintain the –5V output within 3%
tolerance. Figure 14c shows the –5V output voltage regu-
lation versus its own load current when plotted for three
separate load currents on the 5V output. The efficiency of
the dual polarity output converter circuit shown in Figure
14a is given in Figure 14d.
OUTPUT
5V
2A
INPUT
12V
3431 F13
C2
0.22µF
C1
100µF
10V
C
SS
15nF
C
F
220pF
D1
30BQ060
OR B250A
C3
4.7µF
25V
CER
D2
MMSD914TI
L1
15µH
R1
15.4k
R3
2k
C
C
0.022µF
R2
4.99k
R4
47k
L1: CDRH104R-220M
Q1
BOOST BIAS
V
IN
LT3431
SHDN
SYNC
SW
FB
V
C
GND
+
R
C
3.3k
Figure 13. Buck Converter with Adjustable Soft-Start