Datasheet

19
LT3431
sn3431 3431fs
Switch loss:
P
RI V
V
tIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()()()
2
12(/ )
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
36/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW
= Switch resistance (≈0.15) hot
t
EFF
= Effective switch current/voltage overlap time
= (t
r
+ t
f
+ t
Ir
+ t
If
)
t
r
= (V
IN
/1.2)ns
t
f
= (V
IN
/1.1)ns
t
Ir
= t
If
= (I
OUT
/0.05)ns
f = Switch frequency
Example: with V
IN
= 12V, V
OUT
= 5V and I
OUT
= 2A
P
W
PW
PW
SW
BOOST
Q
=+
=+=
==
=+=
−
(. )()()
( • )( / )( )( )( • )
...
()( / )
.
(. ) (. ) .
015 2 5
12
101 10 12 2 12 500 10
025 061 086
5236
12
012
12 0 0015 5 0 003 0 033
2
93
2
Total power dissipation in the IC is given by:
P
TOT
= P
SW
+ P
BOOST
+ P
Q
= 0.86W + 0.12W + 0.03W = 1.01W
Thermal resistance for the LT3431 package is influenced
by the presence of internal or backside planes.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance (θ
JA
) will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
T
J
= T
A
+ (θ
JA
• P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
( )( – )( )
V
F
= Forward voltage of diode (assume 0.52V at 2A)
PW
DIODE
==
(. )( – )()
.
052 12 5 2
12
061
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower V
F
diode can improve efficiency by several percent.
P
INDUCTOR
= (I
LOAD
)
2
(R
IND
)
R
IND
= Inductor DC resistance (assume 0.1Ω)
P
INDUCTOR
(2)
2
(0.1) = 0.4W
Typical thermal resistance of the board is 5°C/W. Taking
the catch diode and inductor power dissipation into ac-
count and using the example calculations for LT3431
dissipation, the LT3431 die temperature will be estimated
as:
T
J
= T
A
+ (θ
JA
• P
TOT
) + [5 • (P
DIODE
+ P
INDUCTOR
)]
With the TSSOP package (θ
JA
= 45°C/W), at an ambient
temperature of 50°C:
T
J
= 50 + (45 • 1.01) + (5 • 1.01) = 101°C
Die temperature can peak for certain combinations of V
IN
,
V
OUT
and load current. While higher V
IN
gives greater
switch AC losses, quiescent and catch diode losses, a
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT3431 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with
minimal device power (low V
IN
and no switching
(V
C
= 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
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