Datasheet

17
LT3431
sn3431 3431fs
APPLICATIO S I FOR ATIO
WUUU
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal elec-
trical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is imple-
mented in the suggested layout of Figure 6. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic in-
ductance produces a flyback spike across the LT3431
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT3431 that may exceed its absolute maximum
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and over-
all noise.
GND GND1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
SYNC
GND
BOOST
V
IN
V
IN
SW
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT3431
C3
C1
D1
C2
D2
3431 F06
C
C
R
C
C
F
L1
MINIMIZE LT3430
C3-D1 LOOP
V
IN
PINS 3 AND 4
ARE SHORTED TOGETHER.
SW PINS 2 AND 5 ARE ALSO
SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND
GND PLANE)
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
SOLDER THE EXPOSED PAD
TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE
GND
V
OUT
V
IN
GND1
2
3
4
5
6 BOOST
V
IN
V
IN
SW
SW
LT3431
R2
R1
CFB
Figure 6. Suggested Layout
3431 F05
5V
L1
V
IN
LT3431
D1C3 C1
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path