Datasheet

LT3430/LT3430-1
20
34301fa
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT3430/LT3430-1 die temperature. If a
more accurate die temperature is required, a measure-
ment of the SYNC pin resistance (to GND) can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.5V at the pin and monitoring the
pin current over temperature in an oven. This should be
done with minimal device power (low V
IN
and no switching
(V
C
= 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC,
due to BOOST pin voltage, can be transferred outside
of the IC to reduce junction temperature, by increasing
the voltage drop in the path of the boost diode D2 (see
Figure 9). This reduction of junction temperature inside
the IC will allow higher ambient temperature operation for
a given set of conditions. BOOST pin circuitry dissipates
power given by:
P
VI V
V
DISS
OUT SW C
IN
BOOST Pin =
()
•/•36
2
Typically V
C2
(the boost voltage across the capacitor C2)
equals V
OUT
. This is because diodes D1 and D2 can be
considered almost equal, where:
V
C2
= V
OUT
– V
FD2
– (–V
FD1
) = V
OUT
Hence the equation used for boost circuitry power dissi-
pation given in the previous Thermal Calculations section
is stated as:
P
VI
V
V
DISS BOOST
OUT SW
IN
OUT()
•/
•=
()
36
Here it can be seen that boost power dissipation increases
as the square of V
OUT
. It is possible, however, to reduce
V
C2
below V
OUT
to save power dissipation by increasing the
voltage drop in the path of D2. Care should be taken that
V
C2
does not fall below the minimum 3.3V boost voltage
required for full saturation of the internal power switch.
For output voltages of 5V, V
C2
is approximately 5V. During
switch turn on, V
C2
will fall as the boost capacitor C2 is
dicharged by the BOOST pin. In the previous BOOST Pin
section, the value of C2 was designed for a 0.7V droop in
V
C2
= V
DROOP
. Hence, an output voltage as low as 4V would
still allow the minimum 3.3V for the boost function using
the C2 capacitor calculated. If a target output voltage of
12V is required, however, an excess of 8V is placed across
the boost capacitor which is not required for the boost
function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by:
PW
BOOST
=
()
=
12 2 36 12
20
04
•/ •
.
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PW
BOOST
=
()
=
12 2 36 5
20
0 167
•/ •
.
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) sav-
APPLICATIONS INFORMATION
BOOST
V
IN
D1
R1
V
OUT
C
F
C
C
LT3430/
LT3430-1
SHDN
SYNC
SW
BIAS
FB
V
C
GND
C2
C1
L1
D2
R2
3430 F09
C3
V
IN
D2 D4
+
R
C
Figure 9. BOOST Pin, Diode Selection