Datasheet

LT3430/LT3430-1
17
34301fa
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
effi ciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a fl yback spike across the LT3430/
LT3430-1 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3430/LT3430-1 that may exceed its
absolute maximum rating. A ground plane should always
be used under the switcher circuitry to prevent interplane
coupling and overall noise.
APPLICATIONS INFORMATION
3430 F05
5
V
L1
V
IN
LT3430/
LT3430-1
D1C3 C1
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
GND GND1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
SYNC
GND
BOOST
V
IN
V
IN
SW
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT3430/
LT3430-1
C3
C1
D1
C2
D2
R2
R1
3430 F06
C
FB
C
F
R
C
C
C
L1
MINIMIZE
LT3430/LT3430-1
C3-D1 LOOP
V
IN
PINS 3 AND 4
ARE SHORTED TOGETHER.
SW PINS 2 AND 5 ARE ALSO
SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND
GND PLANE)
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
SOLDER THE EXPOSED PAD
(PIN 17) TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE
GND
V
OUT
V
IN
GND1
2
3
4
5
6 BOOST
V
IN
V
IN
SW
SW
LT3430/
LT3430-1
Figure 5. High Speed Switching Path
Figure 6. Suggested Layout