Datasheet

LT3071
18
3071fc
For more information www.linear.com/LT3071
APPLICATIONS INFORMATION
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
PWRGD pin is an open-drain NMOS digital output that
actively pulls low if any one of these fault modes is detected:
• V
OUT
is less than 90% of V
OUT(NOMINAL)
on the rising
edge of V
OUT
.
• V
OUT
drops below 85% of V
OUT(NOMINAL)
for more than
25µs.
• V
BIAS
is less than its undervoltage lockout threshold.
• The OUT-to-IN reverse-current detector activates.
• Junction temperature exceeds 145°C typically.*
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
Stability and Output Capacitance
The LT3071’s feedback loop requires an output capacitor
for stability. Choose C
OUT
carefully and mount it in close
proximity to the LT3071’s OUT and GND pins. Include wide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance for
optimal load transient performance. Point-of-load applica
-
tions present the best case layout scenario for extracting
full LT3071 performance.
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3071. Ad-
ditional bulk
capacitors distributed beyond the immediate
decoupling
capacitors are acceptable as their parasitic ESL
and ESR, combined with the distributed PCB inductance
isolates them from the primary compensation pole provided
by the local surface mount ceramic capacitors.
The LT3071 requires a minimum output capacitance of
15µF for stability. LT C strongly recommends that the output
capacitor network consist of several low value ceramic
capacitors in parallel.
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
The LT3071’s unity-gain bandwidth with C
OUT
of 15µF is
about 1MHz at its full-load current of 5A. Surface mounted
MLCC capacitors have a self-resonance frequency of
f
R
= 1/(2π√LC), which must be pushed to a frequency higher
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant frequency greater
than 1MHz, the product 1/(2π√LC) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3071.
REFERENCE
LT3071
IN
V
REF
V
OUT
+
300mV
OUT
VIOC
3071 F02
LOAD
+
–
PWM
SWITCHING REGULATOR
REF
FB
I
TH
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