Datasheet

LT3071
13
3071fc
For more information www.linear.com/LT3071
PIN FUNCTIONS
I
MON
(Pin 21): Output Current Monitor. The I
MON
pin
sources a current typically equal to I
OUT
/2500 or 400µA
per amp of output current. Terminating this pin with a
resistor to GND produces a voltage proportional to I
OUT
.
For example, at I
OUT
= 5A, I
MON
typically sources 2mA.
With a 1k resistor to GND, this produces 2V. If I
MON
is
unused, tie this pin to V
BIAS
.
MARGA (Pin 22): Analog Margining. This pin margins the
output voltage over a continuous analog range of ±10%.
Tying this pin to GND adjusts output voltage by –10%.
Driving this pin to 1.2V adjusts output voltage by +10%. A
voltage source or a voltage output DAC is ideal for driving
this pin. If the MARGA function is not used, either float
this pin or terminate with a 1nF capacitor to GND.
V
O0
, V
O1
and V
O2
(Pins 23, 24, 25): Output Voltage Se-
lect. These three-state pins combine to select a nominal
output
voltage from 0.8V to 1.8V in increments of 50mV.
Output voltage is limited to 1.8V maximum by an internal
override of V
O1
when V
O2
= high. The input logic low
threshold is less than 250mV referenced to GND and the
logic high
threshold is greater than V
BIAS
– 250mV. The
range between these two thresholds as set by a window
comparator defines the logic Hi-Z state. See Table 1 in the
Applications Information section that defines the V
O2
, V
O1
and V
O0
settings versus V
OUT
.
BIAS (Pin 27): Bias Supply. This pin supplies current to
the internal control circuitry and the output stage driving
the pass transistor. The LT3071 requires a minimum 2.2µF
bypass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must satisfy
the following conditions: 2.2V ≤ V
BIAS
≤ 3.6V and V
BIAS
≥
(1.25 • V
OUT
+ 1V). For V
OUT
≤ 0.95V, the minimum BIAS
voltage is limited to 2.2V.
EN (Pin 28): Enable. This pin enables/disables the output
device only. The internal reference and all support functions
are active if V
BIAS
is above its UVLO threshold. Pulling EN
low keeps the reference circuit active, but disables the
output pass transistor and puts the LT3071 into a low
power nap mode. The maximum rising EN threshold is
ratioed to 0.56% of V
BIAS
and the minimum falling ENx
threshold is 0.36% of V
BIAS
. Drive the EN pin with either
a digital logic port or an open-collector NPN or an open-
drain
NMOS terminated with a pull-up resistor to V
BIAS
.
The pull-up resistor must be less than 35k to meet the V
IH
condition of the EN pin. If unused, connect EN to BIAS.
Figure 1. Kelvin Sense Connection
BIAS
LT3071
EN
IN
V
O0
V
O1
V
BIAS
V
IN
V
O2
MARGA
VIOC
SENSE
PWRGD
OUT
I
MON
R
P
REF/BYP
GND
+
+
R
P
3071 F01
LOAD
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