Datasheet

LT3070
16
3070fb
For more information www.linear.com/LT3070
APPLICATIONS INFORMATION
component cost savings. The LT3070 steps to the next
level of performance for the latest generation FPGAs, DSPs
and microprocessors. The simple versatility and benefits
derived from these circuits exceed the power supply needs
of today’s high performance microprocessors.
Programming Output Voltage
Three tri-level input pins, V
O2
, V
O1
and V
O0
, select the
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage resulting from setting these pins
high, low or allowing them to float.
These pins may be tied high or low by either pin-strapping
them to V
BIAS
or driving them with digital ports. Pins that
float may either actually float or require logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
V
O2
, sets the pedestal voltage, and the LSB’s, V
O1
and
V
O0
increment V
OUT
.
Output voltage is limited to 1.8V maximum by an internal
override of V
O1
(default to low) when V
O2
= high.
Table 1: V
O2
to V
O0
Settings vs Output Voltage
V
O2
V
O1
V
O0
V
OUT(NOM)
V
O2
V
O1
V
O0
V
OUT(NOM)
0 0 0 0.80V Z 0 1 1.35V
0 0 Z 0.85V Z Z 0 1.40V
0 0 1 0.90V Z Z Z 1.45V
0 Z 0 0.95V Z Z 1 1.50V
0 Z Z 1.00V Z 1 0 1.55V
0 Z 1 1.05V Z 1 Z 1.60V
0 1 0 1.10V Z 1 1 1.65V
0 1 Z 1.15V 1 X 0 1.70V
0 1 1 1.20V 1 X Z 1.75V
Z 0 0 1.25V 1 X 1 1.80V
Z 0 Z 1.30V
X = Don’t Care, 0 = Low, Z = Float, 1 = High
The input logic low threshold is less than 250mV refer-
enced to GND and the logic high threshold is greater than
V
BIAS
– 250mV. The range between these two thresholds
as set by a window comparator defines the logic Hi-Z
state.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
design includes an internal compensation pole at f
C
=
4kHz. A 10nF REF/BYP capacitor to GND creates a low-
pass pole at f
LP
= 840Hz. The 10nF capacitor decreases
reference voltage noise to about 10µV
RMS
and soft-starts
the reference. The LT3070 only soft-starts the reference
voltage during an initial turn-on sequence. If the EN pin
is toggled low after initial turn-on, the reference remains
powered-up. Therefore, toggling the EN pin from low to
high does not soft-start the reference. Only by turning
the BIAS supply voltage on and off will the reference be
soft-started. Output voltage noise is the RMS sum of the
reference voltage noise in addition to the amplifier noise.
The REF/BYP pin must not be DC loaded by anything except
for applications that parallel other LT3070 regulators for
higher output currents. Consult the Applications Section
on Paralleling for further details.
Output Voltage Margining
Two tri-level input pins, MARGSEL (polarity) and MARGTOL
(scale), select the polarity and amount of output voltage
margining. Margining is programmable in increments of
±1%, ±3% and ±5%. Margining is internally implemented
as a scaling of the reference voltage.
Table 2 illustrates the 2-bit digital word to output voltage
margining resulting from setting these pins high, low or
allowing them to float.
These pins may be set high or low by either pin-strapping
them to V
BIAS
or driving them with digital ports. Pins that
float may either actually float or require logic that has
“Hi-Z” output capability. This allows output voltage to be
dynamically margined if necessary.
The MARGSEL pin determines both the polarity and the ac-
tive state of the margining function. The logic low
threshold
is less than 250mV referenced to GND and enables negative
voltage margining. The logic high threshold is greater than
V
BIAS
– 250mV and enables positive voltage margining.
The voltage range between these two logic thresholds as
set by a window comparator defines the logic Hi-Z state
and disables the margining function.