Datasheet

LT3042
20
3042fb
For more information www.linear.com/LT3042
APPLICATIONS INFORMATION
PCB Layout Considerations
Given the LT3042’s high bandwidth and ultrahigh PSRR,
careful PCB layout must be employed to achieve full
device performance. Figure8 shows an example layout
that delivers full performance of the regulator. Refer to the
LT3042’s DC2246B demo board manual for further details.
Figure8. Example DFN Layout
Table 2. PC Board Trace Resistance
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
2 27.1 13.6
Trace resistance is measured in mΩ/in.
The small worst-case offset of 2mV for each paralleled
LT3042 minimizes the required ballast resistor value.
Figure7 illustrates that two LT3042s, each using a 50mΩ
PCB trace ballast resistor, provide better than 20% ac
-
curate output current sharing at full load. The two 50mΩ
external resistors only add 10mV
of output regulation drop
with a 400mA maximum current. With a 3.3V output, this
only adds 0.3% to the regulation accuracy. As has been
discussed previously, tie the OUTS pin directly to the
output capacitor.
More than two LT3042s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3042s is also useful for distributing heat on the
PCB. For applications with high input-to-output voltage
differential, an input series resistor or resistor in parallel
with the LT3042 can also be used to spread heat.
+
–
100µA
IN
EN/UV
PGFB
GND
OUT
LT3042
ILIM PG
4.7µF
50mΩ
V
OUT
3.3V
I
OUT(MAX)
400mA
3042 F07
16.5k
SET
OUTS
+
–
100µA
IN
EN/UV
PGFB
GND
OUT
LT3042
ILIM PG
4.7µF
50mΩ
10µF
V
IN
5V ±5%
SET
OUTS
0.47µF
Figure7. Parallel Devices
3042 F08
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