Datasheet

LT3030
14
3030fa
For more information www.linear.com/LT3030
applicaTions inForMaTion
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as case size increases.
Linear Technology recommends verifying expected versus
actual capacitance values at operating voltage in situ for
an application.
Figure 2. Ceramic Capacitor
DC Bias Characteristics
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3030 F02
20
0
–20
–40
–60
–80
–100
0
4
8
10
2 6
12
14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 3. Ceramic Capacitor
Temperature Characteristics
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3030 F03
–25 0
50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
V
OUT
500µV/DIV
3030 F04
100ms/DIV
C
OUT
= 10µF
C
BYP
= 0.01µF
I
LOAD
= 750mA
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
the trace's response to light tapping from a pencil, as
shown in Figure 4. Similar vibration induced behavior can
masquerade as increased output voltage noise.
Shutdown/UVLO
The SHDN pin is used to put the LT3030 into a micropower
shutdown state. The LT3030 has an accurate 1.21V
threshold (during turn-on) on the SHDN pin. This threshold
can be used in conjunction with a resistor divider from the
system input supply to define an accurate undervoltage
lockout (UVLO) threshold for the regulator. The SHDN pin
current (at the threshold) needs to be considered when
determining the resistor divider network.
PWRGD Flag
The PWRGD flag indicates that the ADJ pin voltage
is
within 10% of
the regulated voltage. The PWRGD pin is an
open-collector output, capable of sinking 100μA of current
when the ADJ pin voltage is below 90% of the regulated
voltage. There is no internal pull-up on the PWRGD pin;
an external pull-up resistor must be used. As the ADJ
pin voltage rises above 90% of its regulated voltage, the
PWRGD pin switches to a high impedance state and the
external pull-up resistor pulls the PWRGD pin voltage up.
During normal operation, an internal glitch filter prevents
the PWRGD pin from switching to a low voltage state if
the ADJ pin voltage falls below the regulated voltage by
more than 10% in a short transient (<40μs typical) event.
Thermal Considerations
The LT3030’s power handling capability limits the maxi-
mum rated junction temperature (125°C, LT3030E/LT3030I
or 150°C, LT3030H/LT3030MP). Tw o components com-
prise the power dissipated by each channel: