Datasheet

LT3013
14
3013fe
APPLICATIONS INFORMATION
Figure 4 shows a block diagram of the PWRGD circuit. At
startup, the timing capacitor is discharged and the PWRGD
pin will be held low. As the output voltage increases and
the ADJ pin crosses the 90% threshold, the JK fl ip-fl op
is reset, and the 3µA current source begins to charge the
timing capacitor. Once the voltage on the C
T
pin reaches
the V
CT(HIGH)
threshold (approximately 1.7V at 25°C), the
capacitor voltage is clamped and the PWRGD pin is set to
a high impedance state.
During normal operation, an internal glitch fi lter will ignore
short transients (<15µs). Longer transients below the 90%
threshold will reset the JK fl ip-fl op. This fl ip-fl op ensures
that the capacitor on the C
T
pin is quickly discharged all
the way to the V
CT(LOW)
threshold before re-starting the
time delay. This provides a consistent time delay after the
ADJ pin is within 10% of the regulated voltage before the
PWRGD pin switches to high impedance.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C
for LT3013E, LT3013MP or 140°C for LT3013HFE). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential: I
OUT
• (V
IN
– V
OUT
) and,
2. GND pin current multiplied by the input voltage:
I
GND
• V
IN
.
The GND pin current can be found by examining the GND Pin
Current curves in the Typical Performance Characteristics.
Power dissipation will be equal to the sum of the two
components listed above.
The LT3013 has internal thermal limiting designed
to protect the device during overload conditions. For
continuous normal conditions the maximum junction
temperature rating of 125°C (E-grade, MP-grade) or 140°C
(H-grade)must not be exceeded. It is important to give
careful consideration to all sources of thermal resistance
from junction to ambient. Additional heat sources mounted
nearby must also be considered.
QJ
K
V
REF
• 90%
ADJ
V
CT(LOW)
~0.1V
V
CT(HIGH)
– V
BE
(~1.1V)
I
CT
3µA
C
T
3013 F04
–
+
–
+
PWRGD
Figure 4. PWRGD Circuit Block Diagram