Datasheet

LT3013
13
3013fe
APPLICATIONS INFORMATION
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specifi ed with EIA temperature
characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
and temperature coeffi cients as shown in Figures 2
and 3. When used with a 5V regulator, a 16V 10µF Y5V
capacitor can exhibit an effective value as low as 1µF to
2µF for the DC bias voltage applied and over the operating
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and is
available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be signifi cant enough
to drop capacitor values below appropriate levels. Capacitor
DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verifi ed.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress, simi-
lar to the way a piezoelectric accelerometer or microphone
works. For a ceramic capacitor the stress can be induced
by vibrations in the system or thermal transients.
PWRGD Flag and Timing Capacitor Delay
The PWRGD fl ag is used to indicate that the ADJ pin volt-
age is within 10% of the regulated voltage. The PWRGD
pin is an open-collector output, capable of sinking 50µA
of current when the ADJ pin voltage is low. There is no
internal pull-up on the PWRGD pin; an external pull-up
resistor must be used. When the ADJ pin rises to within
10% of its fi nal reference value, a delay timer is started.
At the end of this delay, programmed by the value of the
capacitor on the C
T
pin, the PWRGD pin switches to a high
impedance and is pulled up to a logic level by an external
pull-up resistor.
To calculate the capacitor value on the C
T
pin, use the
following formula:
C
It
VV
TIME
CT DELAY
CT HIGH CT LOW
=
•
–
() ()
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3013 F02
20
0
–20
–40
–60
–80
–100
0
4
8
10
26
12
14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3013 F03
–25 0
50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics