Datasheet

LT1999-10/LT1999-20/
LT1999-50
16
1999fb
applicaTions inForMaTion
Shutdown Capability
If SHDN (Pin 8) is driven to within 0.5V of GND, the LT1999
is placed into a low power shutdown state in which the
part will draw about 3μA from the V
+
supply. The input
pins (+IN and –IN) will draw approximately 1nA if biased
within the range of 0V to 80V (with no differential voltage
applied). If the input pins are pulled below the GND pin,
each input appears as a diode tied to GND in series with
approximately 4k of resistance. The REF pin appears as
approximately 0.4MΩ tied to a mid-supply potential. The
output appears as reverse biased diodes tied between the
output to either V
+
or GND pins.
EMI Filtering and Layout Practices
An internal 1st order differential lowpass noise/EMI sup-
pression filter with a –3dB bandwidth of 10MHz (approxi-
mately 5× the LT1999’s –3dB bandwidth) is included to
help improve the LT1999’s EMI susceptibility and to assist
with the rejection of high frequency signals beyond the
bandwidth of the LT1999 that may introduce errors. The
pole is set by the following equation:
f
filt
= 1/(π•(R
+
IN
+ R
–
IN
)•C
F
) ≈ 10MHz
Both the resistors and capacitors have a ±15% variation
so the pole can vary by approximately ±30% over manu-
facturing process and temperature variations.
The layout for lowest EMI/noise susceptibility is achieved
by keeping short direct connections and minimizing loop
areas (see Figure 4). If the user-supplied sense resistor
cannot be placed in close proximity to the LT1999, the
surface area of the loop comprising connections of +IN
to R
SENSE
and back to –IN should be minimized. This
requires routing PCB traces connecting +IN to R
SENSE
and –IN to R
SENSE
adjacent with one another with minimal
separation. The metal traces connecting +IN to the sense
resistor and –IN to the sense resistor should match and
use the same trace width.
Bypassing the V
+
pin to the GND pin with a 0.1µF capacitor
with short wiring connection is recommended.
Figure 4. Recommended Layout
SUPPLY BYPASS
CAPACITOR
* KEEP LOOP AREA COMPRISING R
SENSE
, +IN AND –IN PINS
AS SMALL AS POSSIBLE.
** REF BYPASS TIED TO A LOW NOISE, LOW IMPEDANCE
SIGNAL GROUND PLANE.
† OPTIONAL 10pF CAPACITOR TO PREVENT dV/dt EDGES
ON INPUT COUPLING TO FLOATING SHDN PIN.
**
*
FROM DC SOURCE
TO LOAD
R
SENSE
DIFFERENTIAL
ANALOG OUT
†
1999 F03
1
2
3
4
8
7
6
5
SHDN
OUT
REF
GND
V
+
+IN
–IN
V
+