Datasheet

LT1993-10
14
199310fb
APPLICATIO S I FOR ATIO
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Large Output Voltage Swings
The LT1993-10 has been designed to provide the 3.2V
P-P
output swing needed by the LTC1748 family of 14-bit
low-noise ADCs. This additional output swing improves
system SNR by up to 4dB. Typical performance curves
and AC specifi cations have been included for these
applications.
Input Bias Voltage and Bias Current
The input pins of the LT1993-10 are internally biased to
the voltage applied to the V
OCM
pin. No external biasing
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the V
OCM
pin
(which sets the output common mode voltage). At both
the positive and negative inputs, any voltage difference is
imposed across 100Ω, generating an input bias current.
For example, if the inputs are tied to 2.5V with the V
OCM
pin at 2.2V, then a total input bias current of 3mA will fl ow
into the LT1993-10’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 3mA will fl ow into
the –INA and –INB inputs.
Application (Demo) Boards
The DC800A Demo Board has been created for stand-alone
evaluation of the LT1993-10 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT1993-10 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the Demo Board section of
this datasheet.
There are also additional demo boards available that
combine the LT1993-10 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
199310 F09
IF IN
LT1993-10
–INA
–INB
V
OCM
2
31
6
7
1
2
+INB
+INA
14
13
15
80.6
16
10
10
LTC22xx
0.1 F
0.1 F
+OUTFILTERED
–OUTFILTERED
AIN
+
AIN
–
4.02k
11k
1.9V
1.5V
3V
V
CM
Figure 9. Level Shifting 3V ADC V
CM
Voltage for
Improved SFDR
3.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
15 16
2
0.50 BSC
0.200 REF
0.00 – 0.05
(UD16) QFN 0904
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 ± 0.05
(4 SIDES)
2.10 ± 0.05
3.50 ± 0.05
0.70 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
PACKAGE DESCRIPTIO
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