Datasheet

LT1977
19
1977fa
APPLICATIO S I FOR ATIO
WUUU
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
the PGFB pin drops below V
PGFB
the C
T
pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
T
pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
current is sourced
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
T
pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
T
= 0.1µF. The PGOOD pin has
Figure 9. Power Good
V
OUT
500mV/DIV
PG
100k TO V
IN
V
CT
500mV/DIV
V
SHDN
2V/DIV
TIME (10ms/DIV)
1977 F09
V
IN
PG
PGFB
LT1977
PG at 80% V
OUT
with 100ms Delay
0.27µF
C
OUT
C
OUT
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1977
V
OUT
Disconnect at 80% V
OUT
with 100ms Delay
0.27µF
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1977
PG at V
IN
> 4V with 100ms Delay
0.27µF
V
OUT
= 3.3V
200k
511k
200k
100k
165k
FB
C
T
V
IN
PG
PGFB
LT1977
V
OUT
Disconnect 3.3V Logic Signal
with 100µs Delay
270pF
200k
V
OUT
= 12V
1977 F10
866k
100k
FB
C
T
C
OUT
C
OUT
Figure 10. Power Good Circuits