Datasheet

LT1976/LT1976B
23
1976bfg
APPLICATIO S I FOR ATIO
WUUU
Figure 12. Suggested Layout
NC
R2
C2
C5
R1
R3
C4
SW
NC
V
IN
NC
BOOST
C
T
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PG
SHDN
SYNC
PGFB
FB
V
C
BIAS
C
SS
1976 F12
C3
GND
GND
D1
L1
V
OUT
C1
C2 D2
MINIMIZE
D1-C3
LOOP
V
IN
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
CONDUCTIVITY
LT1976
Figure 11. High Speed Switching Path
C2 C1
1976 F11
D1
L1
V
IN
LT1976
V
OUT
V
IN
SW
42
HIGH
FREQUENCY
CIRCULATION
PATH
+
LOAD
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1976 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1976 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1976
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.