Datasheet
LT1976/LT1976B
18
1976bfg
APPLICATIO S I FOR ATIO
WUUU
Burst Mode OPERATION (LT1976 ONLY)
To enhance efficiency at light loads, the LT1976 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while mini-
mizing the input quiescent current. During Burst Mode
operation, the LT1976 delivers short bursts of current to
the output capacitor followed by sleep periods where the
output power is delivered to the load by the output capaci-
tor. In addition, V
IN
and BIAS quiescent currents are re-
duced to typically 45μA and 125μA respectively during the
sleep time. As the load current decreases towards a no
load condition, the percentage of time that the LT1976
operates in sleep mode increases and the average input
current is greatly reduced resulting in higher efficiency.
The minimum average input current depends on the V
IN
to
V
OUT
ratio, V
C
frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
III
V
V
III
IN AVG VINS SHDN
OUT
IN
BIASS FB S
()
≅+ +
⎛
⎝
⎜
⎞
⎠
⎟
++
()
()
η
where
I
VINS
= input pin current in sleep mode
V
OUT
= output voltage
V
IN
=
input voltage
I
BIASS
= BIAS pin current in sleep mode
I
FB
= feedback network current
I
S
= catch diode reverse leakage at V
OUT
η = low current efficiency (non Burst Mode operation)
Example: For V
OUT
= 3.3V, V
IN
= 12V
IAA
AA
IN AVG()
.
.
=μ+μ+
⎛
⎝
⎜
⎞
⎠
⎟
μ+ μ+
45 5
33
12
125 12 5 0
..
.
5
08
45 5 47 97
μ
()
()
=μ+μ+μ=μ
A
AA A A
During the sleep portion of the Burst Mode cycle, the V
C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V
OUT
burst ripple is maintained while the average supply current
Figure 6. Burst Mode with Shutdown Pin
V
OUT
50mV/DIV
V
SHDN
2V/DIV
I
SW
500mA/DIV
V
IN
= 12V TIME (50ms/DIV) 1976 G16
V
OUT
= 3.3V
I
Q
= 15μA
Figure 5. I
Q
vs V
IN
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (μA)
50
100
10
20
30 40
1976 F05
50
150
25
75
125
60
V
OUT
= 3.3V
T
A
= 25°C
Figure 4. V
OUT
dV/dt
V
OUT
0.5V/DIV
C
SS
= GND
C
SS
= 0.1μFC
SS
= 0.1μF
C
OUT
= 47μF TIME (1ms/DIV) 1976 F04
I
LOAD
= 200mA
V
IN
= 12V