Datasheet

LT1976/LT1976B
22
1976bfg
APPLICATIO S I FOR ATIO
WUUU
V
IN
PG
PGFB
LT1976
PG at 80% V
OUT
with 100ms Delay
0.27μF
C
OUT
C
OUT
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1976
V
OUT
Disconnect at 80% V
OUT
with 100ms Delay
0.27μF
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1976
PG at V
IN
> 4V with 100ms Delay
0.27μF
V
OUT
= 3.3V
200k
511k
200k
100k
165k
FB
C
T
V
IN
PG
PGFB
LT1976
V
OUT
Disconnect 3.3V Logic Signal
with 100μs Delay
270pF
200k
V
OUT
= 12V
1976 F10
866k
100k
FB
C
T
C
OUT
C
OUT
Figure 10. Power Good Circuits
Figure 9. Power Good
V
OUT
500mV/DIV
PG
100k TO V
IN
V
CT
500mV/DIV
V
SHDN
2V/DIV
TIME (10ms/DIV) 1976 F09
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200μA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
T
pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
T
= 0.1μF. The PGOOD pin has
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT1976 Power Good circuitry.