Datasheet
19
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
WUUU
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
36/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW
= switch resistance (≈0.3) hot
t
EFF
= effective switch current/voltage overlap time
= (t
r
+ t
f
+ t
Ir
+ t
If
)
t
r
= (V
IN
/1.2)ns
t
f
= (V
IN
/1.7)ns
t
Ir
= t
If
= (I
OUT
/0.05)ns
f = switch frequency
Example: with V
IN
= 12V, V
OUT
= 5V and I
OUT
= 1A:
P
W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )
()
=+=
=
()
()
=
=
()
+
()
=
−
03 1 5
12
57 10 1 2 1 12 500 10
0 125 0 171 0 296
5136
12
0 058
12 0 0015 5 0 003 0 033
2
93
2
.
•/ •
...
/
.
...
Total power dissipation in the IC is given by:
P
TOT
= P
SW
+ P
BOOST
+ P
Q
= 0.296W + 0.058W + 0.033W = 0.39W
Thermal resistance for the LT1956 packages is influenced
by the presence of internal or backside planes.
SSOP (GN16) Package: With a full plane under the GN16
package, thermal resistance will be about 85°C/W.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance (θ
JA
) will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance (θ
JA
) number for the desired package an add in
worst-case ambient temperature:
T
J
= T
A
+ (θ
JA
• P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
( )( – )( )
V
F
= Forward voltage of diode (assume 0.63V at 1A)
PW
DIODE
==
(. )( – )()
.
063 12 5 1
12
037
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
low V
F
diode can improve efficiency by several percent.
P
INDUCTOR
= (I
LOAD
)(L
DCR
)
L
DCR
= inductor DC resistance (assume 0.1Ω)
P
INDUCTOR
= (1)(0.1) = 0.1W
Typical thermal resistance of the board is 10°C/W. Taking
the catch diode and inductor power dissipation into ac-
count and using the example calculations for LT1956 dis-
sipation, the LT1956 die temperature will be estimated as:
T
J
= T
A
+ (θ
JA
• P
TOT
) + (10 • [P
DIODE
+ P
INDUCTOR
])
With the GN16 package (θ
JA
= 85°C/W), at an ambient
temperature of 70°C:
T
J
= 70 + (85 • 0.39) + (10 • 0.47) = 108°C
With the TSSOP package (θ
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + (45 • 0.37) + (10 • 0.47) = 91°C
Die temperature can peak for certain combinations of
V
IN
, V
OUT
and load current. While higher V
IN
gives greater
switch AC losses, quiescent and catch diode losses, a
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT1956 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin
current over temperature in a oven. This should be done
with minimal device power (low V
IN
and no switching
[V
C
= 0V]) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.