Datasheet

17
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
WUUU
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1956
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate volt-
ages across the LT1956 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1956
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Figure 6. Suggested Layout
GND GND
SHDN
SYNC
GND
BOOST
V
IN
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT1956
C3
C1
D1
C2
D2
R2
R1
1956 F06
C
FB
C
F
R
C
C
C
L1
MINIMIZE LT1956
C3-D1 LOOP
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
GND
V
OUT
V
IN
FOR THE FE PACKAGE,
SOLDER THE EXPOSED
PAD TO THE COPPER
GROUND PLANE
UNDERNEATH THE DEVICE
1956 F05
5V
L1
V
IN
LT1956
D1 C1C3
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path