LT1956/LT1956-5 High Voltage, 1.5A, 500kHz Step-Down Switching Regulators U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT ®1956/LT1956-5 are 500kHz monolithic buck switching regulators with an input voltage capability up to 60V. A high efficiency 1.5A, 0.2Ω switch is included on the die along with all the necessary oscillator, control and logic circuitry. A current mode architecture provides fast transient response and good loop stability. Wide Input Range: 5.5V to 60V 1.
LT1956/LT1956-5 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Voltage (VIN) ................................................. 60V BOOST Pin Above SW ............................................ 35V BOOST Pin Voltage ................................................. 68V SYNC, SENSE Voltage (LT1956-5) ........................... 7V SHDN Voltage ........................................................... 6V BIAS Pin Voltage ....................................................
LT1956/LT1956-5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX Switch Current Limit VC Open, Boost = VIN + 5V, FB = 1V or VSENSE = 4.1V ● 1.5 2 3 A Switch On Resistance ISW = 1.5A, Boost = VIN + 5V (Note 7) 0.2 0.3 0.
LT1956/LT1956-5 U W TYPICAL PERFOR A CE CHARACTERISTICS FB Pin Voltage and Current Switch Peak Current Limit SHDN Pin Bias Current 1.234 2.0 250 TYPICAL 2.0 GUARANTEED MINIMUM 1.5 1.5 1.224 VOLTAGE 1.219 1.0 CURRENT 1.214 150 100 12 0 20 40 60 DUTY CYCLE (%) 100 80 6 1.204 50 100 25 75 –50 –25 0 JUNCTION TEMPERATURE (°C) 1956 G01 0 50 100 –50 –25 25 75 0 JUNCTION TEMPERATURE (°C) Shutdown Supply Current 300 40 LOCKOUT VSHDN = 0V 1.2 0.8 START-UP 0.
LT1956/LT1956-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Minimum Input Voltage with 5V Output Switching Frequency 7.5 575 VOUT = 5V L = 18µH 40 525 500 475 BOOST PIN CURRENT (mA) 7.0 INPUT VOLTAGE (V) FREQUENCY (kHz) 550 BOOST Pin Current 45 MINIMUM INPUT VOLTAGE TO START 6.5 6.0 MINIMUM INPUT VOLTAGE TO RUN 5.5 450 35 30 25 20 15 10 5 –25 0 25 50 75 100 5.0 125 0 JUNCTION TEMPERATURE (°C) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 LOAD CURRENT (A) 1956 G10 2.
LT1956/LT1956-5 U U U PI FU CTIO S GND (Pins 1, 8, 9, 16): The GND pin connections act as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pins of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pins and the load ground. Keep the paths between the GND pins and the load ground short and use a ground plane when possible.
LT1956/LT1956-5 W BLOCK DIAGRA The LT1956 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO FEEDBACK PIN FUNCTIONS The feedback (FB) pin on the LT1956 is used to set output voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the FB pin. Please read both parts before committing to a final design.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO LT1956 VSW TO FREQUENCY SHIFTING 1.4V ERROR AMPLIFIER + – L1 OUTPUT 5V Q1 1.2V R1 R4 2k R3 1k FB + C1 BUFFER R2 Q2 TO SYNC CIRCUIT VC GND 1956 F02 Figure 2. Frequency and Current Limit Foldback with high input voltage. High frequency pickup will increase and the protection accorded by frequency and current foldback will decrease. 10mV/DIV VOUT USING 22µF CERAMIC OUTPUT CAPACITOR 10mV/DIV VOUT USING 100µF, 0.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Peak-to-peak output ripple voltage is the sum of a triwave (created by peak-to-peak ripple current (ILP-P) times ESR) and a square wave (created by parasitic inductance (ESL) and ripple current slew rate). Capacitive reactance is assumed to be small compared to ESR or ESL.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of operation, but errs only slightly on the high side for discontinuous mode, so it can be used for all conditions.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO solution. The maximum output load current in discontinuous mode, however, must be calculated and is defined later in this section. Discontinuous mode is entered when the output load current is less than one-half of the inductor ripple current (ILP-P). In this mode, inductor current falls to zero before the next switch turn-on (see Figure 8).
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO where: f = switching frequency tON = switch minimum on time VF = diode forward voltage VIN = input voltage I • R = inductor I • R voltage drop If this condition is not observed, the current will not be limited at IPK, but will cycle-by-cycle ratchet up to some higher value. Using the nominal LT1956 clock frequency of 500KHz, a VIN of 12V and a (VF + I • R) of say 0.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Output capacitor ripple current (RMS): IRIPPLE(RMS) = 0.29(VOUT )(VIN – VOUT ) (L)( f)(VIN ) Ceramic Capacitors Ceramic capacitors are generally chosen for their good high frequency operation, small size and very low ESR (effective series resistance). Their low ESR reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capacitors.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO internal switch will ramp up VIN current into the diode in an attempt to get it to recover. Then, when the diode has finally turned off, some tens of nanoseconds later, the VSW node voltage ramps up at an extremely high dV/dt, perhaps 5 to even 10V/ns ! With real world lead inductances, the VSW node can easily overshoot the VIN rail. This can result in poor RFI behavior and if the overshoot is severe enough, damage the IC itself.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO RFB L1 LT1956 2.38V IN INPUT OUTPUT VSW + STANDBY RHI – 5.5µA + SHDN C1 + TOTAL SHUTDOWN RLO C2 0.4V – GND 1956 F04 Figure 4. Undervoltage Lockout bypassed with a 1000pF capacitor to prevent coupling problems from the switch node. If hysteresis is desired in the undervoltage lockout point, a resistor RFB can be added to the output node. Resistor values can be calculated from: R HI = [ RLO VIN − 2.38 ( ∆V/ VOUT + 1) + ∆V ( 2.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO LAYOUT CONSIDERATIONS LT1956 As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Board layout also has a significant effect on thermal resistance. For the GN package, Pins 1, 8, 9 and 16, GND, are a continuous copper plate that runs under the LT1956 die. This is the best thermal path for heat out of the package. Reducing the thermal resistance from Pins 1, 8, 9 and 16 onto the board will reduce die temperature and increase the power capability of the LT1956.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Boost current loss: PDIODE = VOUT2 (IOUT / 36) PBOOST = VIN VF = Forward voltage of diode (assume 0.63V at 1A) Quiescent current loss: PDIODE = PQ = VIN (0.0015) + VOUT (0.003) PINDUCTOR = (ILOAD)(LDCR) LDCR = inductor DC resistance (assume 0.1Ω) PINDUCTOR = (1)(0.1) = 0.1W Example: with VIN = 12V, VOUT = 5V and IOUT = 1A: PSW ( ) ( 57 •10 −9 (1/ 2)(1)(12 ) 500 •10 3 12 = 0.125 + 0.171 = 0.296W ) (5) (1 / 36) = 0.058W 2 PBOOST = (0.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Note: Some of the internal power dissipation in the IC, due to BOOST pin voltage, can be transferred outside of the IC to reduce junction temperature by increasing the voltage drop in the path of the boost diode D2 (see Figure 9). This reduction of junction temperature inside the IC will allow higher ambient temperature operation for a given set of conditions.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO Input Voltage vs Operating Frequency Considerations The absolute maximum input supply voltage for the LT1956 is specified at 60V. This is based on internal semiconductor junction breakdown effects. The practical maximum input supply voltage for the LT1956 may be less than 60V due to internal power dissipation or switch minimum on time considerations.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO 80 180 LT1956 60 SW CFB 40 R1 FB TANTALUM – + RO 200k 1.22V ESR RLOAD CERAMIC ESL + C1 VC 120 20 90 PHASE 0 60 –20 30 PHASE (DEG) ERROR AMPLIFIER gm = 2000µmho GND 150 GAIN OUTPUT GAIN (dB) CURRENT MODE POWER STAGE gm = 2mho C1 R2 RC –40 CF CC 1956 F10 Figure 10. Model for Loop Response oscillations.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO MMSD914TI D3 10MQ060N REMOVABLE INPUT C2 0.1µF BOOST VIN SW LT1956 R3 54k L1 18µH 5V, 1A BIAS R1 15.4k SHDN FB SYNC GND R4 25k D1 10MQ060N VC C3 2.2µF R2 4.99k + ALTERNATE SUPPLY C1 100µF 10V CF 220pF RC 2.2k CC 0.022µF 1956 F12 Figure 12. Dual Source Supply with 25µA Reverse Leakage D2 MMSD914TI BOOST INPUT 12V C3 2.2µF CERAMIC C2 0.1µF BIAS VIN L1 18µH SW D1 LT1956 SHDN SYNC GND + R1 15.4k FB R2 4.99k VC Q1 RC 2.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO D2 MMSD914TI C2 0.1µF L1* 15µH BOOST VIN 9V TO 12V (TRANSIENTS TO 36V) VOUT1** 5V SW VIN LT1956 R1 15.4k SHDN C3 2.2µF 50V CERAMIC SYNC C5 10µF 6.3V CER + FB GND R2 4.99k VC RC 2.2k CC 3300pF CF 220pF D1 B0540W GND C4 10µF *SUMIDA CDRH4D28-150 6.3V **SEE FIGURE 14c FOR VOUT1, VOUT2 CER LOAD CURRENT RELATIONSHIP † IF LOAD CAN GO TO ZERO, AN OPTIONAL PRELOAD OF 500Ω CAN BE USED TO IMPROVE REGULATION + C6 10µF 6.
LT1956/LT1956-5 U W U U APPLICATIO S I FOR ATIO current in L2 and C4 flows via the catch diode D3, charging the negative output capacitor C6. If the negative output is not loaded enough, it can go severely unregulated (become more negative). Figure 14b shows the maximum allowable –5V output load current (vs load current on the 5V output) that will maintain the –5V output within 3% tolerance.
LT1956/LT1956-5 U PACKAGE DESCRIPTIO Minimum inductor continuous mode: LMIN = (VIN )(VOUT ) (V + VF ) 2(f)(VIN + VOUT )IP – IOUT 1 + OUT VIN For a 12V to –12V converter using the LT1956 with peak switch current of 1.5A and a catch diode of 0.63V: ICONT > (12)2 (1.5)2 = 0.370 A 4(12 + 12)(12 + 12 + 0.63) For a load current of 0.25A, this says that discontinuous mode can be used and the minimum inductor needed is found from: 2(12)(0.25) LMIN = = 5.3µH (500 • 103 )(1.
LT1956/LT1956-5 U PACKAGE DESCRIPTIO FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BB 4.90 – 5.10* (.193 – .201) 3.58 (.141) 3.58 (.141) 16 1514 13 12 1110 6.60 ±0.10 9 2.94 (.116) 4.50 ±0.10 SEE NOTE 4 2.94 6.40 (.116) BSC 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD LAYOUT 1.10 (.0433) MAX 4.30 – 4.50* (.169 – .177) 0° – 8° 0.09 – 0.20 (.0036 – .0079) 0.45 – 0.75 (.018 – .030) NOTE: 1.
LT1956/LT1956-5 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 .009 (0.229) REF 16 15 14 13 12 11 10 9 .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 .053 – .068 (1.351 – 1.727) 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .
