Datasheet

LT1952/LT1952-1
18
19521fe
(A) V
IN
> 14.25* (7.75V LT1952-1), and
(B) SD_V
SEC
> 1.32V, and
(C) OC < 107mV, and
(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)
*V
IN
> 8.75V (6.5V LT1952-1) is ok for latch reset if the latch
was only set by overcurrent condition in (3) above.
SS_MAXDC Discharge Timing
It can be seen in Figure 10 that two types of discharge
can occur for the SS_MAXDC pin. In timing (A) the fault
that caused the soft-start event has been removed before
SS_MAXDC falls to 0.45V. This means the soft-start
latch will be reset when SS_MAXDC falls to 0.45V and
SS_MAXDC will begin charging. In timing (B), the fault that
caused the soft-start event is not removed until some time
after SS_MAXDC has fallen past 0.45V. The SS_MAXDC
pin continues to discharge to 0.2V and remains low until
all faults are removed.
The time for SS_MAXDC to fall to a given voltage can be
approximated as:
SS_MAXDC (t
FALL
) =
(C
SS
/I
DIS
)•[SS_MAXDC(DC)–V
SS(MIN)
]
where:
I
DIS
= net discharge current on C
SS
C
SS
= capacitor value at SS_MAXDC pin
SS_MAXDC(DC) = programmed DC voltage
V
SS(MIN)
= minimum SS_MAXDC voltage before
recharge
I
DIS
~ 8e
–4
+ (V
REF
– V
SS(MIN)
)[(1/2R
B
) – (1/R
T
)]
For faults arising from (1) and (2),
V
REF
= 100mV.
For a fault arising from (3),
V
REF
= 2.5V.
SS_MAXDC(DC) = V
REF
[R
B
/(R
T
+ R
B
)]
V
SS(MIN)
= SS_MAXDC reset threshold = 0.45V
(if fault removed before t
FALL
)
APPLICATIONS INFORMATION
Example:
For an overcurrent fault (OC > 100mV), V
REF
= 2.5V,
R
T
= 35.7k, R
B
= 100k, C
SS
= 0.1µF and assume
V
SS(MIN)
= 0.45V,
I
DIS
~ 8e
–4
+(2.5–0.45)[(1/2•100k)–(1/35.7k)]
= 8e
–4
+ (2.05)(–0.23e
–4
) = 7.5e
–4
SS_MAXDC(DC) = 1.84V
SS_MAXDC (t
FALL
) = (1e – 7/7.5e
–4
)•(1.84–0.45)
= 1.85e–4 s
If the OC fault is not removed before 185µs then SS_MAXDC
will continue to fall past 0.45V towards a new V
SS(MIN)
.
The typical V
OL
for SS_MAXDC at 150µA is 0.2V.
SS_MAXDC Charge Timing
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 11.
The ability to predict SS_MAXDC rise time between any two
voltages allows prediction of several key timing periods:
(1)No Switching Period
(time from SS_MAXDC(DC) to V
SS(MIN)
+ time from
V
SS(MIN)
to V
SS(ACTIVE)
)
(2)Converter Output Rise Time
(time from V
SS(ACTIVE)
to V
SS(REG)
; V
SS(REG)
is the
level of SS_MAXDC where maximum duty cycle
clamp equals the natural duty cycle of the switch)
(3)Time For Maximum Duty Cycle Clamp within X% of
Target Value
The time for SS_MAXDC to charge to a given voltage V
SS
is found by re-arranging: