Datasheet

LT1952/LT1952-1
10
19521fe
TIMING DIAGRAM
BLOCK DIAGRAM
1952 F01
t
DELAY
: PROGRAMMABLE SYNCHRONOUS DELAY
FAULTS TRIGGERING SOFT-START
V
IN
< 8.75V
OR
SD_V
SEC
< 1.32V (UVLO)
OR
OC > 107mV (OVERCURRENT)
SOFT-START LATCH RESET:
V
IN
> 14.25V (> 8.75V IF LATCH SET BY OC)
AND
SD_V
SEC
> 1.32V
AND
OC < 107mV
AND
SS_MAXDC < 0.45V
SOFT-START
LATCH SET
SOUT
OUT
SS_MAXDC
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
0.2V
V
REF
>90%
–
+
–
+
+
–
SOURCE
2.5mA
2.5V
1.23V
(100 TO 500)kHz
OSC
(TYPICAL 200kHz)
I
HYST
10µA SD_V
SEC
= 1.32V
0µA SD_V
SEC
> 1.32V
7
5
14
13
6
3
4
10
81 92
SD_V
SEC
R
OSC
SYNC
1.32V
1.23V
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
(LINEAR)
SLOPE COMP
8µA 0% DC
35µA 80% DC
RAMP
S
Q
R
R
Q
S
BLANK
FB COMP GND BLANK
12
DELAY
V
REF
15
V
IN
SS_MAXDC
SOFT-START CONTROL
OUT
16
SOUT
PGND
I
SENSE
11
OC
DRIVER
±1A
±50mA
12V
13V
0.45V
1952 BD
–
+
–
+
(VOLTAGE)
ERROR AMPLIFIER
107mV
0mV TO 220mV
ON
DELAY
V
IN
ON
V
IN
OFF
LT1952
I
START
= 460µA
V
IN
ON = 14.25V
V
IN
OFF = 8.75V
LT1952-1
I
START
= 400µA
V
IN
ON = 7.75V
V
IN
OFF = 6.5V
START-UP
INPUT CURRENT (ISTART)
–
+
+
–
SENSE
CURRENT
+
–
OVER
CURRENT
Figure 1. Timing Diagram
Figure 2. Block Diagram