Datasheet

LT1809/LT1810
16
180910fa
APPLICATIONS INFORMATION
Rail-to-Rail Characteristics
The LT1809/LT1810 have an input and output signal range
that includes both negative and positive power supply.
Figure 1 depicts a simplifi ed schematic of the amplifi er.
The input stage is comprised of two differential amplifi ers,
a PNP stage Q1/Q2 and a NPN stage Q3/Q4 that are active
over different ranges of common mode input voltage. The
PNP differential pair is active for common mode voltages
between the negative supply to approximately 1.5V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer
the tail current I
1
to the current mirror Q6/Q7, activating
the NPN differential pair and causing the PNP pair to
become inactive for the rest of the input common mode
range up to the positive supply.
A pair of complementary common emitter stages
Q14/Q15 form the output stage, enabling the output to
swing from rail-to-rail. The capacitors C1 and C2 form
the local feedback loops that lower the output impedance
at high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1809/LT1810 amplifi ers combine high speed with
large output current in a small package, so there is a need
to ensure that the die’s junction temperature does not
exceed 150°C. The LT1809 is housed in an SO-8 package
or a 6-lead SOT-23 package and the LT1810 is in an SO-8
or 8-lead MSOP package. All packages have the V
–
sup-
ply pin fused to the lead frame to enhance the thermal
conductance when connecting to a ground plane or a large
metal trace. Metal trace and plated through-holes can be
used to spread the heat generated by the device to the
backside of the PC board. For example, on a 3/32" FR-4
board with 2oz copper, a total of 660 square millimeters
connected to Pin 4 of LT1810 in an SO-8 package (330
square millimeters on each side of the PC board) will bring
the thermal resistance, θ
JA
, to about 85°C/W. Without
extra metal trace connected to the V
–
pin to provide a heat
sink, the thermal resistance will be around 105°C/W. More
information on thermal resistance for all packages with
various metal areas connecting to the V
–
pin is provided
in Tables 1, 2 and 3 for thermal consideration.
Figure 1. LT1809 Simplifi ed Schematic Diagram
Q4
Q6
Q3
Q7
Q10
Q1
Q13 Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2
ESDD1
+IN
–IN
ESDD3
ESDD4
V
+
V
+
Q8
R2R1
R3 R4 R5
Q14
1809 F01
I
2
C2
C
C
V
–
C1
BUFFER
AND
OUTPUT BIAS
Q17
Q16
ESDD5
SHDN
V
+
R7
100k
R6
10k
D9
V
+
V
–
V
–
V
–
V
–
ESDD6
BIAS
GENERATION