Datasheet

14
LT1803/LT1804/LT1805
180345f
If both amplifiers are loaded simultaneously, then the total
power dissipation is 0.19W.
The maximum ambient temperature that the part is al-
lowed to operate is:
T
A
= T
J
– (P
DMAX
• 190°C/W)
= 150°C – (0.190W • 190°C/W) = 113.9°C
Similar calculations can be carried out for specific pack-
ages and conditions.
Also worth noting, the DD package includes a low θ
JA
underside metal which is internally connected to V
S
–
. If the
underside metal is properly soldered to a PCB, the θ
JA
of
the part will be close to 50°C/W. This θ
JA
is significantly
less than leaving the underside metal unattached and can
be useful for certain applications.
Input Offset Voltage
The input offset voltage will change greatly based upon
which input stage is active. The PNP input stage is active
from the negative supply voltage to about 1.3V below the
positive supply rail, then the NPN input stage is activated
for the remaining input range up to the positive supply rail
during which the PNP stage remains inactive. The offset
voltage is typically less than 1000µV in the range the PNP
input stage is active.
Input Bias Current
The LT1803/LT1804/LT1805 employ a patent-pending
technique to reduce the input bias current to less than 1µA
for the input common mode voltage range of 0.2V above
the negative supply rail to 1.75V below the positive rail.
The low input offset voltage and low input bias current
provide precision performance in high source impedance
applications.
Output
The LT1803/LT1804/LT1805 can deliver a large output
current, so the short-circuit current limit is set around
50mA to prevent damage to the device. Attention must be
paid to keep the junction temperature of the IC below the
absolute maximum rating of 150°C (refer to the Power
Dissipation section) when the output is continuously short
circuited. The output of the amplifier has reverse-biased
diodes connected to each supply. If the output is forced
beyond either supply, unlimited current will flow through
these diodes. If the current is transient and limited to less
than 100mA and the total supply voltage is less than
APPLICATIO S I FOR ATIO
WUUU
Figure 1. LT1803/LT1804/LT1805 Simplified Schematic Diagram
Q4
Q18Q17
Q16
Q6
Q3
Q7
Q10
Q1
Q13 Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2ESDD1
+IN
–IN
V
–
ESDD3ESDD4
V
+
V
+
V
–
Q8
R2R1
R3 R4 R5
Q14
180345 F01
+
I
2
+
I
3
C2
C
C
V
–
+
C1
BUFFER
AND
OUTPUT BIAS
V
+
V
–
Q19