Datasheet

6
LT1796
1796f
FU CTIO TABLES
U
U
Driver Output
INPUTS BUS TERMINALS
TXD R
S
CANH CANL OPERATING STATE
0V
RS
< 3V High Low Dominant
0V
RS
> 4V Hi-Z Hi-Z Standby
1V
RS
< 3V Hi-Z Hi-Z Recessive
1V
RS
> 4V Hi-Z Hi-Z Standby
Receiver Output
BUS VOLTAGE
V
BUS
= V
CANH
– V
CANL
R
S
RXD RESPONSE TIME
V
BUS
< 0.5V <3V High Fast
0.5V ≤ V
BUS
≤ 0.9V <3V Indeterminate Fast
V
BUS
> 0.9V <3V Low Fast
V
BUS
< 0.5V >4V High Slow
0.5V ≤ V
BUS
≤ 0.9V >4V Indeterminate Slow
V
BUS
> 0.9V >4V Low Slow
TI I G DIAGRA S
WUW
2.5V
V
DIFF
= V
CANH
– V
CANL
5V
TXD
0V
V
DIFF
V
DIFFLO
V
DIFFHI
25%
50%
1796 F02
t
TXDOFF
t
TXDON
2.5V
Figure 2. Driver Delay Waveforms
2.5V
5V
TXD
0V
RXD
0V
2V
0.8V
1796 F03
t
LBOFF
t
LBON
2.5V
Figure 3. Loopback Delay Waveforms
3V
CANL = 2.5V
3.5V
CANH
2.5V
RXD
0.8V
2V
1796 F04
t
RXDON
t
RXDOFF
3V
Figure 4. Reciever Delay Waveforms
2.5V
5V
R
S
0V
RXD
0.8V
1796 F05
t
WAKE
Figure 5. Wake Up from Standby Waveforms
TEST CIRCUIT
5V
0.1µF
7
3
1
46
1796 F01
R
S
100pF
285
30pF
TXD
RXD
CANH
CANL
R
S
V
REF
GND
60Ω
Figure 1. Switching Test Circuit
BLOCK DIAGRA
W
RX
CANH
CANL
1796 BD
GND
V
REF
SLOPE/
STANDBY
REFERENCE
VOLTAGE
DRIVER
V
CC
3
7
6
2
5
RXD
4
R
S
8
TXD
1