Datasheet

LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
13
1767fb
For more information www.linear.com/LT1767
applicaTions inForMaTion
Figure 6. Typical Application and Suggested Layout (Topside Only Shown)
BOOST
LT1767-2.5
V
IN
OUTPUT
2.5V
1.2A
V
IN
12V
1767 F06a
C2
0.1µF
C
C
1.5nF
R
C
4.7k
D1
UPS120
C1
10µF
CERAMIC
C3
2.2µF
CERAMIC
D2
CMDSH-3
L1
5µH
V
SW
FBSHDN
OPEN
OR
HIGH
= ON
GND
V
C
SYNC
V
IN
GND
R
C
C
C
V
OUT
C1
C3
C2
L1
1767 F06
SYNC
SHDN
KELVIN SENSE
V
OUT
CONNECT TO
GROUND PLANE
MINIMIZE LT1767,
C3, D1 LOOP
KEEP FB AND V
C
COMPONENTS
AWAY FROM
HIGH INPUT
COMPONENTS
PLACE FEEDTHROUGHS
AROUND GROUND PIN
AND UNDER GROUND PAD
FOR GOOD THERMAL
CONDUCTIVITY
D2
D1
GND
THERMAL CALCULATIONS
Power dissipation in the LT1767 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following
formulas show
how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
P
SW
=
R
SW
I
OUT
( )
2
V
OUT
( )
V
IN
+17ns I
OUT
( )
V
IN
( )
f
( )
Boost current loss for V
BOOST
= V
OUT
:
P
BOOST
=
V
OUT
2
I
OUT
/ 50
( )
V
IN
Quiescent current loss:
P
Q
=
V
IN
0.001
( )
R
SW
= Switch resistance (≈0.27Ω when hot)
17ns = Equivalent switch
current/voltage overlap time
f = Switch frequency
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