Datasheet

12
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
sn1767 1767fas
APPLICATIONS INFORMATION
WUU
U
Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W.
Thermal resistance for LT1767 package is influenced by
the presence of internal or backside planes. With a full
plane under the package, thermal resistance for the
exposed pad package will be about 40°C/W. No plane will
increase resistance to about 150°C/W. To calculate die
temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
T
J
= T
A
+ θ
JA
(P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
()
−
()()
V
F
= Forward voltage of diode (assume 0.5V at 1A)
PW
DIODE
=
()
−
()()
=
05 12 5 1
12
029
.
.
Figure 6. Typical Application and Suggested Layout (Topside Only Shown)
BOOST
LT1767-2.5
V
IN
OUTPUT
2.5V
1.2A
V
IN
12V
1767 F06a
C2
0.1µF
C
C
1.5nF
R
C
4.7k
D1
UPS120
C1
10µF
CERAMIC
C3
2.2µF
CERAMIC
D2
CMDSH-3
L1
5µH
V
SW
FBSHDN
OPEN
OR
HIGH
= ON
GND
V
C
SYNC
V
IN
GND
R
C
C
C
V
OUT
C1
C3
C2
L1
1767 F06
SYNC
SHDN
KELVIN SENSE
V
OUT
CONNECT TO
GROUND PLANE
MINIMIZE LT1767,
C3, D1 LOOP
KEEP FB AND V
C
COMPONENTS
AWAY FROM
HIGH INPUT
COMPONENTS
PLACE FEEDTHROUGHS
AROUND GROUND PIN
AND UNDER GROUND PAD
FOR GOOD THERMAL
CONDUCTIVITY
D2
D1
GND