Datasheet

LT1766/LT1766-5
23
1766fc
APPLICATIONS INFORMATION
the V
C
control voltage to the point where some sort of
cycle-skipping or odd/even cycle behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and
high f
OSC
can result in an unacceptably short minimum
switch on-time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more diffi cult the circuit will
be to stabilize. This is true of almost all high frequency
analog circuits, read the Layout Considerations section
fi rst. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V
C
compensation
to a ground track carrying signifi cant switch current. In
addition, the theoretical analysis considers only fi rst order
non-ideal component behavior. For these reasons, it is
important that a fi nal stability check is made with produc-
tion layout and components.
The LT1766 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1766 can be considered as two g
m
blocks, the error
amplifi er and the power stage.
Figure 11 shows the overall loop response. At the V
C
pin, the frequency compensation components used are:
R
C
= 2.2k, C
C
= 0.022μF and C
F
= 220pF. The output
capacitor used is a 100μF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a use-
ful zero in the loop frequency response for maintaining
stability. This ESR, however, contributes signifi cantly to
the ripple voltage at the output (see Output Ripple Volt-
age in the Applications Section). It is possible to reduce
capacitor size and output ripple voltage by replacing the
tantalum output capacitor with a ceramic output capaci-
tor because of its very low ESR. The zero provided by the
tantalum output capacitor must now be reinserted back
into the loop. Alternatively there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor,
R
C,
at the V
C
pin in series with the compensation capaci-
tor, C
C
or by placing a capacitor, C
FB
, between the output
and the FB pin.
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
–20
–40
PHASE (DEG)
180
150
120
90
60
30
0
1766 F11
GAIN
PHASE
10
V
IN
= 42V
V
OUT
= 5V
I
LOAD
= 500mA
C
OUT
= 100μF, 10V, 0.1Ω
1k 10k 1M100 100k
R
C
= 2.2k
C
C
= 22nF
C
F
= 220pF
Figure 11. Overall Loop Response
–
+
1.22V
V
SW
V
C
LT1766
GND
1766 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000μmho
+
TANTALUM
C
FB
CERAMIC
ESL
C1
Figure 10. Model for Loop Response