Datasheet

LT1766/LT1766-5
18
1766fc
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface ca-
pacitance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired
in the undervoltage lockout point, a resistor, R
FB
, can
be added to the output node. Resistor values can be
calculated from:
R
RV VV V
RA
RRV V
HI
LO IN OUT
LO
FB HI OUT
=
−+
()
+
[]
−
()
=
()
()
238 1
238 55
./
..
/
ΔΔ
Δ
μ
25k suggested for R
LO
V
IN
= Input voltage at which switching stops as input
voltage descends to trip level
ΔV = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless input
rises back to 13.5V. ΔV is therefore 1.5V and V
IN
= 12V.
Let R
LO
= 25k.
R
k
kA
k
k
Rk k
HI
FB
=
−+
()
+
[]
μ
()
=
()
=
=
()
=
25 12 2 38 1 5 5 1 1 5
238 25 55
25 10 41
224
116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to
initial operating frequency up to 700kHz. This means
that
minimum practical sync frequency is equal to the
worst-case
high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuffi cient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maxi-
mum effi ciency, switch rise and fall times are typically
in the nanosecond range. To prevent noise both radiated
and conducted, the high speed switching current path,
shown in Figure 5, must be kept as short as possible.
This is implemented in the suggested layout of Figure 6.
Shortening this path will also reduce the parasitic trace
inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a fl yback spike across the
LT1766 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1766 that may exceed its absolute
1766 F05
5V
L1
V
IN
LT1766
D1 C1C3
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path
APPLICATIONS INFORMATION