Datasheet

LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
13
1765fd
APPLICATIONS INFORMATION
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 2A:
P
W
PW
PW
SW
BOOST
Q
=
( )()()
+
()
()( )
()
=+ =
=
()( )
=
=
()
=
−
013 2 5
10
17 10 2 10 1 25 10
026 043 069
5250
10
01
10 0 001 0 01
2
96
2
.
•.•
...
/
.
..
Total power dissipation, P
TOT
, is 0.69 + 0.1 + 0.01 = 0.8W.
Thermal resistance for the LT1765 16-lead TSSOP exposed
pad package is infl uenced by the presence of internal or
backside planes. With a full plane under the package,
thermal resistance will be about 45°C/W. With no plane
under the package, thermal resistance will increase to
about 110°C/W. For the exposed pad package θ
JC(PAD)
=
10°C/W. Thermal resistance is dominated by board perfor-
mance. To calculate die temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T
J
= T
A
+ θ
JA (PTOT)
When estimating ambient, remember the nearby catch
diode will also be dissipating power.
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
()
−
()()
V
F
= Forward voltage of diode (assume 0.5V at 2A)
PW
DIODE
=
()
−
()()
=
05 10 5 2
10
05
.
.
Notice that the catch diode’s forward voltage contributes
a signifi cant loss in the overall system effi ciency. A larger,
lower V
F
diode can improve effi ciency by several percent.
Typical thermal resistance of the board θ
B
is 35°C/W. At
an ambient temperature of 25°C,
T
J
= T
A
+ θ
JA
(P
TOT
) + θ
B
(P
DIODE
)
T
J
= 25 + 45 (0.8) + 35 (0.5) = 79°C
DIE TEMPERATURE MEASUREMENT
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must fi rst be calibrated, with
no signifi cant output load, in an oven. An initial value of
40k with a temperature coeffi cient of 0.16%/°C is typical.
The same measurement can then be used in operation to
indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more diffi cult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section fi rst.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode, and connecting the V
C
compensation to a
ground track carrying signifi cant switch current. In addition,
the theoretical analysis considers only fi rst order ideal
component behavior. For these reasons, it is important
that a fi nal stability check is made with production layout
and components.
The LT1765 uses current mode control. This alleviates many
of the phase shift problems associated with the inductor.
The basic regulator loop is shown in Figure 7, with both
tantalum and ceramic capacitor equivalent circuits. The
LT1765 can be considered as two g
m
blocks, the error
amplifi er and the power stage.
Figure 7. Model for Loop Response
–
+
1.2V
V
SW
V
C
LT1765
GND
1765 F07
R1
OUTPUT
ESR
C
F
C
C
R
C
500k
ERROR
AMPLIFIER
FB
R2
C1
CURRENT MODE
POWER STAGE
g
m
= 5mho
g
m
=
850
μmho
+
ESL
CERAMICTANTALUM
C1