Datasheet
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
12
1765fd
APPLICATIONS INFORMATION APPLICATIONS INFORMATION
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and
overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1765
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability
or subharmonic like oscillation.
Board layout also has a signifi cant effect on thermal
resistance. The exposed pad or GND pin is a continuous
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be
seen by the low θ
JC
of the exposed pad package. Reduc-
ing the thermal resistance from Pin 4 or exposed pad
onto the board will reduce die temperature and increase
the power capability of the LT1765. This is achieved by
providing as much copper area as possible around this
pin/pad. Also, having multiple solder fi lled feedthroughs
to a continuous copper plane under LT1765 will help in
reducing thermal resistance. Ground plane is usually suit-
able for this purpose. In multilayer PCB designs, placing a
ground plane next to the layer with the LT1765 will reduce
thermal resistance to a minimum.
THERMAL CALCULATIONS
Power dissipation in the LT1765 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit cur-
rent, and input quiescent current. The following formulas
show how to calculate each of these losses. These formulas
assume continuous mode operation, so they should not
be used for calculating effi ciency at light load currents.
Switch loss:
P
RI V
V
ns I V f
SW
SW OUT OUT
IN
OUT IN
=
()( )
+
()()()
2
17
Boost current loss for VBOOST = VOUT:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
50/
Quiescent current loss:
PV
QIN
=
()
0 001.
R
SW
= Switch resistance (≈0.13Ω at hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Figure 6. Typical Application and Layout (Topside Only Shown)
BOOST
LT1765-33
V
IN
OUTPUT
3.3V
2.5A
INPUT
15V
1765 F06
C2
0.18μF
C
C
2.2nF
D1
B220A
C1
4.7μF
CERAMIC
C3
4.7μF
CERAMIC
D2
CMDSH-3
L1
2.7μH
V
SW
FBSHDN
ONOFF
GND
V
C
SYNC
GND
KEEP FB AND V
C
COMPONENTS AND
TRACES AWAY FROM
HIGH FREQUENCY,
HIGH INPUT
COMPONENTS
PLACE FEEDTHROUGHS
UNDER AND AROUND
GROUND PAD FOR
GOOD THERMAL
CONDUCTIVITY
1765 F6a
GND
MINIMIZE D1, C3
LT1765 LOOP
C3
D2
C2
L1
KELVIN
SENSE
V
OUT
D1
C1
V
IN
V
OUT
C
C