Datasheet

10
LT1762 Series
1762fa
GND (Pin 4): Ground.
SHDN (Pin5): Shutdown. The SHDN pin is used to put the
LT1762 regulators into a low power shutdown state. The
output will be off when the SHDN pin is pulled low. The
SHDN pin can be driven either by 5V logic or open-
collector logic with a pull-up resistor. The pull-up resistor
is required to supply the pull-up current of the open-
collector gate, normally several microamperes, and the
SHDN pin current, typically 1µA. If unused, the SHDN pin
must be connected to V
IN
. The device will be in low power
shutdown state if the SHDN pin is not connected.
IN (Pin 8): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if the
device is more than six inches away from the main input
filter capacitor. In general, the output impedance of a
battery rises with frequency, so it is advisable to include a
bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF is sufficient. The
LT1762 regulators are designed to withstand reverse
voltages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if a
battery is plugged in backwards, the device will act as if
there is a diode in series with its input. There will be no
reverse current flow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
OUT (Pin 1): Output. The output supplies power to the
load. A minimum output capacitor of 2.2µF is required to
prevent oscillations. Larger output capacitors will be
required for applications with large transient loads to limit
peak voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
SENSE (Pin 2): Output Sense. For fixed voltage versions
of the LT1762 (LT1762-2.5/LT1762-3/LT1762-3.3/
LT1762-5), the SENSE pin is the input to the error ampli-
fier. Optimum regulation will be obtained at the point
where the SENSE pin is connected to the OUT pin of the
regulator. In critical applications, small voltage drops are
caused by the resistance (R
P
) of PC traces between the
regulator and the load. These may be eliminated by con-
necting the SENSE pin to the output at the load as shown
in Figure 1 (Kelvin Sense Connection). Note that the
voltage drop across the external PC traces will add to the
dropout voltage of the regulator. The SENSE pin bias
current is 10µA at the nominal rated output voltage. The
SENSE pin can be pulled below ground (as in a dual supply
system where the regulator load is returned to a negative
supply) and still allow the device to start and operate.
ADJ (Pin 2): Adjust. For the adjustable LT1762, this is the
input to the error amplifier. This pin is internally clamped
to ±7V. It has a bias current of 30nA which flows into the
pin (see curve of ADJ Pin Bias Current vs Temperature in
the Typical Performance Characteristics). The ADJ pin
voltage is 1.22V referenced to ground and the output
voltage range is 1.22V to 20V.
BYP (Pins 3): Bypass. The BYP pin is used to bypass the
reference of the LT1762 regulators to achieve low noise
performance from the regulator. The BYP pin is clamped
internally to ±0.6V (one V
BE
). A small capacitor from the
output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01µF can be
used for reducing output voltage noise to a typical 20µV
RMS
over a 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
PIN FUNCTIONS
UUU
IN
SHDN
1762 F01
R
P
OUT
V
IN
SENSE
GND
LT1762
R
P
4
2
1
5
8
+
+
LOAD
Figure 1. Kelvin Sense Connection