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LT1738

1738fa

The LT

1738 is a switching regulator controller designed

to lower conducted and radiated electromagnetic interfer-

ence (EMI). Ultralow noise and EMI are achieved by

controlling the voltage and current slew rates of an exter-

nal N-channel MOSFET switch. Current and voltage slew

rates can be independently set to optimize harmonic

content of the switching waveforms vs efficiency. The

LT1738 can reduce high frequency harmonic power by as

much as 40dB with only minor losses in efficiency.

The LT1738 utilizes a current mode architecture opti-

mized for single switch topologies such as boost, flyback

and Cuk. The IC includes gate drive and all necessary

oscillator, control and protection circuitry. Unique error

amp circuitry can regulate both positive and negative

voltages. The internal oscillator may be synchronized to

an external clock for more accurate placement of switch-

ing harmonics.

Protection features include gate drive lockout for low V

soft-start, output current limit, short-circuit current limit-

ing, gate drive overvoltage clamp and input supply

undervoltage lockout.

■

Greatly Reduced Conducted and Radiated EMI

■

Low Switching Harmonic Content

■

Independent Control of Output Switch Voltage and

Current Slew Rates

■

Greatly Reduced Need for External Filters

■

Single N-Channel MOSFET Driver

■

20kHz to 250kHz Oscillator Frequency

■

Easily Synchronized to External Clock

■

Regulates Positive and Negative Voltages

■

Easier Layout Than with Conventional Switchers

■

Power Supplies for Noise Sensitive Communication

Equipment

■

EMI Compliant Offline Power Supplies

■

Precision Instrumentation Systems

■

Isolated Supplies for Industrial Automation

■

Medical Instruments

■

Data Acquisition Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Ultralow Noise 5V to 12V Converter

101113

SHDN

CAP

NFB

LT1738

GND

14 2

GCL

SYNC

GATE

CSL

VSL

PGND

5pF

Si9426

10nF

1.5k

3.3k

25k

3.3k

16.9k

1.3nF

22nF

0.22µF

21.5k

2.5k

10µH

OPTIONAL

150µF

OSCON

4 × 150µF

OSCON

12V

MBRD620

100µF

22µH

1738 TA01

25mΩ

12V Output Noise

(Bandwidth = 100MHz)

400µV

P-P

5µs/DIV

1738 TA01a

Slew Rate Controlled

Ultralow Noise DC/DC Controller

APPLICATIO S

FEATURES

TYPICAL APPLICATIO

DESCRIPTIO

POINT B

ON SCHEMATIC

50mV/DIV

POINT A

ON SCHEMATIC

500µV/DIV

Summary of content (20 pages)

PAGE 1
LT1738 Slew Rate Controlled Ultralow Noise DC/DC Controller U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT ®1738 is a switching regulator controller designed to lower conducted and radiated electromagnetic interference (EMI). Ultralow noise and EMI are achieved by controlling the voltage and current slew rates of an external N-channel MOSFET switch. Current and voltage slew rates can be independently set to optimize harmonic content of the switching waveforms vs efficiency.
PAGE 2
LT1738 W U PACKAGE/ORDER I FOR ATIO U W W W ABSOLUTE U AXI U RATI GS (Note 1) Supply Voltage (VIN) ................................................ 20V Gate Drive Current ..................................... Internal Limit V5 Current ................................................. Internal Limit SHDN Pin Voltage .................................................... 20V Feedback Pin Voltage (Trans. 10ms) ...................... ±10V Feedback Pin Current ............................................
PAGE 3
LT1738 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and other pins open unless otherwise noted.
PAGE 4
LT1738 U W TYPICAL PERFOR A CE CHARACTERISTICS Negative Feedback Voltage and Input Current vs Temperature 2.480 3.2 1.258 700 2.485 3.0 1.256 650 2.490 2.8 1.254 600 1.252 550 2.495 2.6 1.250 500 2.500 2.4 1.248 450 2.505 2.2 1.246 400 2.510 2.0 1.244 350 1.242 300 2.515 1.8 1.240 –50 –25 0 NEGATIVE FEEDBACK VOLTAGE (V) 750 2.520 –50 –25 250 25 50 75 100 125 150 TEMPERATURE (°C) 0 1.
PAGE 5
LT1738 U W TYPICAL PERFOR A CE CHARACTERISTICS SHDN Pin Hysteresis Current vs Temperature 27 21 19 17 0 25 50 75 100 125 150 TEMPERATURE (°C) VIN = 20 RVSL, RCSL = 17k 14 13 VIN = 12 RVSL, RCSL = 17k 0.2 GATE DRIVE A/B PIN VOLTAGE (V) PERCENT OF MAX CS VOLTAGE 80 70 60 40 60 DUTY CYCLE (%) 80 100 10.6 GCL = 12V 10.5 6.5 0.50 6.4 0.45 6.2 10.3 6.1 VIN = 12V NO LOAD 10.2 6.0 10.1 5.9 10.0 5.8 GCL = 6V 9.90 5.7 9.80 5.6 9.70 –50 –25 9.3 0.25 0.20 0.15 0.10 0.05 5.
PAGE 6
LT1738 U U U PI FU CTIO S Part Supply V5 (Pin 5): This pin provides a 5V output that can sink or source 10mA for use by external components. V5 source current comes from VIN . Sink current goes to GND. VIN must be greater than 6.5V in order for this voltage to be in regulation. If this pin is used, a small capacitor (<1µF) may be placed on this pin to reduce noise. This pin can be left open if not used. GND (Pin 11): Signal Ground.
PAGE 7
LT1738 U U U PI FU CTIO S Approximately 50µA of current can be sourced from this pin if VGCL < VIN – 0.8V. This pin also controls undervoltage lockout of the gate drive. If the pin is tied to a zener or voltage source, the gate drive will not be enabled until VIN > VGCL + 0.8V. If this pin is tied to VIN, then undervoltage lockout is disabled. There is an internal 19V zener tied from this pin to ground to provide a fail-safe for maximum gate voltage.
PAGE 8
LT1738 U U U PI FU CTIO S TEST CIRCUITS VC (Pin 12): The compensation pin is used for frequency compensation and current limiting. It is the output of the error amplifier and the input of the current comparator. Loop frequency compensation can be performed with an RC network connected from the VC pin to ground. The voltage on VC is proportional to the switch peak current. The normal range of voltage on this pin is 0.25V to 1.27V.
PAGE 9
LT1738 U OPERATIO In noise sensitive applications switching regulators tend to be ruled out as a power supply option due to their propensity for generating unwanted noise. When switching supplies are required due to efficiency or input/output constraints, great pains must be taken to work around the noise generated by a typical supply.
PAGE 10
LT1738 U OPERATIO The current slew feedback loop consists of the voltage across the external sense resistor, which is internally amplified and differentiated. The derivative is limited to a value set by RCSL. The current slew rate is thus inversely proportional to both the value of sense resistor and RCSL. The two control loops are combined internally so that a smooth transition from current slew control to voltage slew control is obtained. When turning on, the driver current will slew before voltage.
PAGE 11
LT1738 U OPERATIO Table 1. Safety and Protection Features FEATURE FUNCTION EFFECT on GATE DRIVER SLEW CONTROL EFFECT on VC, SS Maximum Current Fault Turn Off FET at Maximum Switch Current (VSENSE = 0.1) Immediately Goes Low Overridden None Short-Circuit Fault Turn Off FET and Reset VC for Short-Circuit (VSENSE = 0.22) Immediately Goes Low Overridden Discharge VC, SS to GND Overvoltage Fault Turn Off Driver If FB > VREG + 0.
PAGE 12
LT1738 U W U U APPLICATIO S I FOR ATIO Oscillator frequency is important for noise reduction in two ways. First the lower the oscillator frequency the lower the waveform’s harmonics, making it easier to filter them. Second the oscillator will control the placement of the output voltage harmonics which can aid in specific problems where you might be trying to avoid a certain frequency bandwidth. Oscillator Sync If a more precise frequency is desired (e.g.
PAGE 13
LT1738 U U W U APPLICATIO S I FOR ATIO R1 Table 2 VOUT FB PIN INPUT VOLTAGE CAPACITOR VALUE < 25V R2 5pF 50V 2.5pF 100V 1pF Smaller value capacitors can be made in two ways. The first is simply combining two capacitors in series. The equivalent capacitance is then (C1 • C2)/(C1 + C2). The second method makes use of a capacitor divider. Care should be taken that the voltage rating of the capacitor satisfies the full voltage swing thus essentially the same rating as the MOSFET.
PAGE 14
LT1738 U W U U APPLICATIO S I FOR ATIO most of the control circuitry of the regulator. Note after the control circuitry powers on, gate driver activity will depend on the voltage of VIN with respect to the voltage on GCL. As the SHDN pin enables the internal regulator a 24µA current will be sourced from the pin that can provide hysteresis for undervoltage lockout. This hysteresis can be used to prevent part shutdown due to input voltage sag from an initial high current draw.
PAGE 15
LT1738 U W U U APPLICATIO S I FOR ATIO Setting Current Limit The sense resistor sets the value for maximum operating current. When the CS pin voltage is 0.1V the gate driver will immediately go low (no slew control). Therefore the sense resistor value should be set to RS = 0.1V/ISW(PEAK), where ISW(PEAK) is the peak current in the MOSFET. ISW(PEAK) will depend on the topology and component values and tolerances. Certainly it should be set below the saturation current value for the inductor.
PAGE 16
LT1738 U W U U APPLICATIO S I FOR ATIO The following procedure can be used to handle these trade-offs: 1. Assume that the average inductor current for a boost converter is equal to load current times VOUT/VIN and decide whether the inductor must withstand continuous overload conditions. If average inductor current at maximum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 1.5A overload condition.
PAGE 17
LT1738 U W U U APPLICATIO S I FOR ATIO The worst component from an AC point is the gate charge current. The actual peak current depends on gate capacitance and slew rate, being higher for larger values of each. The total current can be estimated by gate charge and frequency of operation. Because of the slewing with this part gate charge is spread out over a longer time period than with a normal FET driver. This reduces capacitance requirements.
PAGE 18
LT1738 U W U U APPLICATIO S I FOR ATIO First determine the maximum gate drive that you require. Typically you will want it to be at least 2V greater than the rated threshold. Higher voltages will lower the on resistance and increase efficiency. Be certain to check the maximum allowed gate voltage. Often this is 20V but for some logic threshold MOSFETs it is only 8V to 10V. VGCL needs to be set approximately 0.2V above the desired max gate threshold. In addition VIN needs to be at least 1.
PAGE 19
LT1738 U U W U APPLICATIO S I FOR ATIO There are two other loops to pay attention to. The current slew involves a high bandwidth control that goes through the MOSFET switch, the sense resistor and into the CS pin of the part and out the GATE pin to the MOSFET. Trace inductance and resistance should be kept low on the GATE drive trace. The CS trace should have low inductance. MORE HELP AN70 contains information about low noise switchers and measurement of noise and should be consulted.
PAGE 20
LT1738 U TYPICAL APPLICATIO Ultralow Noise 30W Offline Power Supply DANGER: HIGH VOLTAGE L1 X1 + 1M 0.1µF 250VAC “X2” 1M 90VAC TO 264VAC BR1 100µF 400V P6KE200A 1 100k 2W VBIAS + 510k 17 56µF 35V VIN 14 5 510k 6 1.8nF 7 165k 165k 10Ω 8 19.6k 2N2222 3.9k 3.9k 16 15 9 19 NC D4 BA521 10 NFB 470pF D1 A1 +VOUT 12V 2.