Datasheet

LT1719
11
1719fa
APPLICATIONS INFORMATION
The outputs of the LT1719 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1719 can drive DC
terminations of 200Ω or more, but lower characteristic
impedance traces can be used with series termination or
AC termination topologies.
Shutdown Control
The LT1719 features a shutdown control pin for reduced
quiescent current when the comparator is not needed.
During shutdown, the inputs and the outputs become high
impedances. The LT1719 is enabled when the shutdown
input is pulled low with a threshold roughly two diode drops
below +V
S
or V
+
. Therefore, if driven by a standard TTL
gate, a pull-up resistor should be used. Because shutdown
is active high, this resistor adds little power drain during
shutdown. A logic high disables the comparator. The
LT1719S8 logic interface is based on the output power
rails, +V
S
and GND.
For applications that do not use the shutdown feature,
it may be helpful to tie the shutdown control to ground
through a 100Ω resistor rather than directly. This allows
the SHDN pin to be pulled high during debug or in-circuit
test (bed of nails) so that the output node can be wiggled
without damaging the low impedance output driver of
the LT1719.
The shutdown state is not guaranteed to be useful as a
multiplexer. Digital signals can have extremely fast edge
rates that may be enough to momentarily activate the
LT1719 output stage via internal capacitive coupling. No
damage to the LT1719 will result, but this could prove
deleterious to the intended recipient of the signal.
The LT1719 includes a FET pull-up on the shutdown control
pin (see the Simplifi ed Schematic) as well as other inter-
nal structures to make the shutdown state current drain
<<1μA. Shutdown is guaranteed with an open circuit on the
shutdown control pin. When the shutdown control pin is
driven to +V
S
/V
+
– 0.5V, the 70kΩ linear region impedance
of the pull-up FET will cause a current fl ow of 7μA (typ)
into the +V
S
/V
+
pin and out the shutdown pin. Currents in
all other power supply terminals will be <1μA.
Power Supply Sequencing
The LT1719S8 is designed to tolerate any power supply
sequencing at system turn-on and power down. In any
of the previously shown power supply confi gurations, the
various supplies can activate in any order without exces-
sive current drain by the LT1719.
As always, the Absolute Maximum Ratings must not be
exceeded, either on the power supply terminals or the input
terminals. Power supply sequencing problems can occur
when input signals are powered from supplies that are
independent of the LT1719’s supplies. For the compara-
tor inputs, the signals should be powered from the same
V
CC
and V
EE
supplies as the LT1719. For the shutdown
input, the signal should be powered from the same +V
S
as the LT1719.
Hysteresis
The LT1719 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.
The input-output transfer characteristic is illustrated in
Figure 3 showing the defi nitions of V
OS
and V
HYST
based
upon the two measurable trip points. The hysteresis band
makes the LT1719 well behaved, even with slowly moving
inputs.
Figure 3. Hysteresis I/O Characteristics
V
HYST
(= V
TRIP
+
– V
TRIP
–
)
V
HYST
/2
V
OL
1719 F03
V
OH
V
TRIP
–
V
TRIP
+
ΔV
IN
= V
IN
+
– V
IN
–
V
TRIP
+
+ V
TRIP
–
2
V
OS
=
V
OUT
0