Datasheet

LT1715
14
1715fa
Of course, if the V
EE
of the LT1715 is the same as the
ECL negative supply, the GND pin can be tied to it as well
and +V
S
grounded. Then the output stage has the same
powerrails as the ECL and the circuits of Figure 8b can
be used.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,with
most layouts. Avoid the temptation to use speed up capaci-
tors. Not only can they foul up the operation of the ECL
gate because of overshoots, they can damage the ECL
inputs, particularly during power-up of separate supply
confi gurations.
The level translator designs assume one gate load. Multiple
gates can have signifi cant I
IH
loading, and the transmis-
sion line routing and termination issues also make this
case diffi cult.
APPLICATIONS INFORMATION
Figure 8
5V
5V
180Ω
DO NOT USE FOR LT1715
LEVEL TRANSLATION. SEE TEXT
270Ω
820Ω
10KH/E
R2
+V
S
R3
R1
10KH/E
100K/E
+V
S
5V OR 5.2V
4.5V
R1
510Ω
620Ω
R2
180Ω
180Ω
R3
750Ω
510Ω
(a) STANDARD TTL TO PECL TRANSLATOR
(b) LT1715 OUTPUT TO PECL TRANSLATOR
LSTTL
1/2 LT1715
V
EE
V
CC
V
EE
V
CC
R2
V
ECL
3V
R3R4
R1
10KH/E
100K/E
V
ECL
5V OR 5.2V
4.5V
R1
300Ω
330Ω
R2
180Ω
180Ω
R3
OMIT
1500Ω
(c) 3V LT1715 OUTPUT TO PECL TRANSLATOR
1/2 LT1715
R4
560Ω
1000Ω
R4
V
ECL
+V
S
V
CC
V
EE
R3
1715 F08
R2
R1
ECL FAMILY
10KH/E
V
ECL
–5.2V
R1
560Ω
270Ω
+V
S
5V
3V
R2
270Ω
510Ω
R3
330Ω
300Ω
(d) LT1715 OUTPUT TO STANDARD ECL TRANSLATOR
1/2 LT1715
R4
1200Ω
330Ω
100K/E –4.5V
680Ω
330Ω
5V
3V
270Ω
390Ω
300Ω
270Ω
1500Ω
430Ω
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