Datasheet

7
LT1614
OPERATIO
U
When Q1 turns off during the second phase of switching,
the SWX node voltage abruptly increases to (V
IN
+ |V
OUT
|).
The SW node voltage increases to V
D
(about 350mV). Now
current in the first loop, begining at C1, flows through L1,
C2, D1 and back to C1. Current in the second loop flows
from C3 through L2, D1 and back to C3. Load current
continues to be supplied by L2 and C3.
An important layout issue arises due to the chopped
nature of the currents flowing in Q1 and D1. If they are both
tied directly to the ground plane before being combined,
switching noise will be introduced into the ground plane.
It is almost impossible to get rid of this noise, once present
in the ground plane. The solution is to tie D1’s cathode to
the ground pin of the LT1614 before the combined cur-
rents are dumped into the ground plane as drawn in
Figures 4, 5 and 6. This single layout technique can
virtually eliminate high frequency “spike” noise so often
present on switching regulator outputs.
Output ripple voltage appears as a triangular waveform
riding on V
OUT
. Ripple magnitude equals the ripple current
of L2 multiplied by the equivalent series resistance (ESR)
of output capacitor C3. Increasing the inductance of L1
and L2 lowers the ripple current, which leads to lower
output voltage ripple. Decreasing the ESR of C3, by using
ceramic or other low ESR type capacitors, lowers output
ripple voltage. Output ripple voltage can be reduced to
arbitrarily low levels by using large value inductors and
low ESR, high value capacitors.
Figure 5. Switch-On Phase of Inverting Converter. L1 and L2 Current Have Positive dI/dt
Figure 6. Switch-Off Phase of Inverting Converter. L1 and L2 Current Have Negative dI/dt
+
+
L1 L2
C2
–(V
IN
+ V
OUT
)
SW SWX
D1
Q1
1614 F05
C1 C3 R
LOAD
–V
OUT
V
IN
V
CESAT
+
+
L1 L2
C2
V
IN
+ V
OUT
+ V
D
SW SWX
D1
Q1
1614 F06
C1 C3 R
LOAD
–V
OUT
V
IN
V
D