Datasheet

19
LT1506
APPLICATIONS INFORMATION
WUU
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Figure 10. Response from V
C
Pin to Output
FREQUENCY (Hz)
GAIN (µMho)
PHASE (DEG)
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100 10k 100k 10M
1506 F11
1k 1M
GAIN
PHASE
R
OUT
200k
C
OUT
12pF
V
C
ERROR AMPLIFIER EQUIVALENT CIRCUIT
R
LOAD
= 50Ω
V
FB
2 × 10
–3
)(
Figure 11. Error Amplifier Gain and Phase
Figure 12. Overall Loop Characteristics
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R
C
) in series with the
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R
C
may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R
C
where gain margin falls to zero is:
R Loop
V
G G ESR
C
OUT
MP MA
Gain =1
()
=
()()()()
242.
FREQUENCY (Hz)
GAIN: V
C
PIN TO OUTPUT (dB)
PHASE: V
C
PIN TO OUTPUT (DEG)
40
20
0
–20
–40
40
0
–40
–80
–120
10 1k 10k 1M
1505 F10
100 100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V
I
OUT
= 2A
FREQUENCY (Hz)
LOOP GAIN (dB)
LOOP PHASE (DEG)
80
60
40
20
0
–20
200
150
100
50
0
–50
10 1k 10k 1M
1505 F12
100 100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V, I
OUT
= 2A
C
OUT
= 100µF, 10V, AVX TPS
C
C
= 1.5nF, R
C
= 0, L = 10µH
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 2000µMho, with an output imped-
ance of 200kΩ in parallel with 12pF. In all practical
applications, the compensation network from V
C
pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
error amplifier a pole at 530Hz, with phase rolling off to 90°
and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
shows a two-pole characteristic until the ESR of the output
capacitor brings it back above 10kHz. Phase margin is
about 60° at unity-gain.
Analog experts will note that around 4.4kHz, phase dips
very close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
(≥ ±3:1).