Datasheet

LT1355/LT1356
11
13556fc
APPLICATIONS INFORMATION
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a ca-
pacitive load (or a low value resistive load) the network is
incompletely bootstrapped and adds to the compensation
at the high impedance node. The added capacitance slows
down the amplifier which improves the phase margin by
moving the unity-gain frequency away from the pole formed
by the output impedance and the capacitive load. The zero
created by the RC combination adds phase to ensure that
even for very large load capacitances, the total phase lag
can never exceed 180 degrees (zero phase margin) and
the amplifier remains stable.
Power Dissipation
The LT1355/LT1356 combine high speed and large output
drive in small packages. Because of the wide supply volt-
age range, it is possible to exceed the maximum junction
temperature under certain conditions. Maximum junction
temperature (T
J
) is calculated from the ambient or case
temperature (T
A
or T
C
) and power dissipation (P
D
) as
follows:
LT1355CN8: T
J
= T
A
+ (P
D
• 130°C/W)
LT1355CS8: T
J
= T
A
+ (P
D
• 190°C/W)
LT1356CN: T
J
= T
A
+ (P
D
• 110°C/W)
LT1356CS: T
J
= T
A
+ (P
D
• 150°C/W)
LT1356HS: T
J
= T
C
+ (P
D
• 30°C/W)
Worst-case power dissipation occurs at the maximum
supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
1/2 supply voltage). For each amplifier P
DMAX
is:
P
DMAX
= (V
+
– V
–
)(I
SMAX
) + (V
+
/2)
2
/R
L
Example: LT1356 in S16 at T
A
= 70°C, V
S
= ±15V, R
L
= 1k
P
DMAX
= (30V)(1.45mA) + (7.5V)
2
/1kΩ = 99.8mW
T
JMAX
= 70°C + (4 • 99.8mW)(150°C/W) = 130°C
SIMPLIFIED SCHEMATIC
1355/1356 SS01
OUT
+IN
–IN
V
+
V
–
R1
800Ω
C
C
R
C
C