Datasheet

8
LT1339
sn1339 1339fas
OPERATION
U
Basic Control Loop
The LT1339 uses a constant frequency, current mode
synchronous architecture. The timing of the IC is provided
through an internal oscillator circuit, which can be syn-
chronized to an external clock, programmable to operate
at frequencies up to 150kHz. The oscillator creates a
modified sawtooth wave at its timing node (CT) with a slow
charge, rapid discharge characteristic.
During typical positive buck operation, the main switch
MOSFET is enabled at the start of each oscillator cycle. The
main switch stays enabled until the current through the
switched inductor, sensed via the voltage across a series
(Refer to Functional Block Diagram)
sense resistor (R
SENSE
), is sufficient to trip the current
comparator (IC1) and, in turn, reset the RS latch. When the
RS latch resets, the main switch is disabled, and the
synchronous switch MOSFET is enabled. Shoot-through
prevention logic prohibits enabling of the synchronous
switch until the main switch is fully disabled. If the current
comparator threshold is not obtained throughout the
entire oscillator charge period, the RS latch is bypassed
and the main switch is disabled during the oscillator
discharge time. This “minimum off time” assures ad-
equate charging of the bootstrap supply, protects the main
switch, and is typically about 1µs.
+
–
–
+
1.25V
SOFT START
8µA
SS
I
AVG
V
C
–
+
–
+
EA
1.25V
5V
REFERENCE
V
FB
0.5µA
× 15
CURRENT
SENSE AMP
IC1
SR
Q
OSC
SL/ADJ
NONOVERLAPPING
SWITCH LOGIC
UVLO
CIRCUIT
CT
TG
V
BOOST
PHASE
12V
IN
TS
BG
SENSE
+
V
IN
5V
REF
MAIN
SWITCH
SYNC
SWITCH
SENSE
–
R
SENSE
V
OUT
1339 • BD
CIRCUIT
ENABLE
+
–
2.5V
PGNDSGND
+
ONE SHOT
50k
AVERAGE
CURRENT
LIMIT
RUN/SHDN
5V
REF
V
REF
SYNC
UU
W
FU CTIO AL BLOCK DIAGRA