Datasheet

12
LT1339
sn1339 1339fas
APPLICATIONS INFORMATION
WUU
U
the converter input supply is enabled with no voltage on
the LT1339 12V
IN
pin, the LT1339 driver output clamps
will not be activated. To prevent turn-on, an external
current path must be used to bleed off charge on the
switch MOSFET gates. High value bleed resistors (50k to
250k) should be connected between the TG and SW pins
and between BG and PGND. This provides discharge paths
for the switch MOSFET gates, preventing parasitic turn-on
and damage to the MOSFETs.
Inductor Selection
The inductor for an LT1339 converter is selected based on
output power, operating frequency and efficiency require-
ments. Generally, the selection of inductor value can be
reduced to desired maximum ripple current in the inductor
(∆I). For a buck converter, the minimum inductor value for
a desired maximum operating ripple current can be deter-
mined using the following relation:
L
VVV
If V
MIN
OUT IN OUT
OIN
=
()
−
()
()()( )
∆
where f
O
= operating frequency. Given an inductor value
(L), the peak inductor current is the sum of the average
inductor current (I
AVG
)and half the inductor ripple current
(∆I), or:
II
VVV
Lf V
PK AVG
OUT IN OUT
OIN
=+
()
−
()
()()( )( )
2
The inductor core type is determined by peak current and
efficiency requirements. The inductor core must with-
stand peak current without saturating, and series winding
resistance and core losses should be kept as small as is
practical to maximize conversion efficiency.
The LT1339 peak current limit threshold is 40% greater than
the average current limit threshold. Slope compensation
effects reduce this margin as duty cycle increases. This
margin must be maintained to prevent peak current limit
from corrupting the programmed value for average current
limit. Programming the peak ripple current to less than 15%
of the desired average current limit value will assure porper
operation of the average current limit feature through 90%
duty cycle (see Slope Compensation section).
Oscillator Synchronization
The LT1339 oscillator generates a modified sawtooth
waveform at the C
T
pin between low and high thresholds
of about 0.8V (vl) and 2.5V (vh) respectively. The oscillator
can be synchronized by driving a TTL level pulse into the
SYNC pin. This inputs to a one-shot circuit that reduces the
oscillator high threshold to 2V for about 200ns. The SYNC
input signal should have minimum high/low times of ≥1µs.
0.8V
1339 F04
2V
2.5V
(vl)
SYNC
V
CT
(vh)
FREE RUN SYNCHRONIZED
Figure 4. Free Run and Synchronized Oscillator
Waveforms (at C
T
Pin)
Slope Compensation
Current mode switching regulators that operate with a
duty cycle greater than 50% and have continuous inductor
current can exhibit duty cycle instability. While a regulator
will not be damaged and may even continue to function
acceptably during this type of subharmonic oscillation, an
irritating high-pitched squeal is usually produced.
The criterion for current mode duty cycle instability is met
when the increasing slope of the inductor ripple current is
less than the decreasing slope, which is the case at duty
cycles greater than 50%. This condition is illustrated in
Figure 5a. The inductor ripple current starts at I
1
, at the
beginning of each oscillator switch cycle. Current
increases at a rate S1 until the current reaches the control
trip level I
2
. The controller servo loop then disables the
main switch (and enables the synchronous switch) and
inductor current begins to decrease at a rate S2. If the
current switch point (I
2
) is perturbed slightly and
increased by ∆I, the cycle time ends such that the mini-
mum current point is increased by a factor of (1 + S2/S1)
to start the next cycle. On each successive cycle, this error
is multiplied by a factor of S2/S1. Therefore, if S2/S1 is
≥ 1, the system is unstable.