Datasheet

7
LT1310
sn1310 1310fs
C
T
Selection for Operating Frequency
To synchronize to an external input signal, the timing
capacitor and PLL filter components must be chosen
properly. This is a simple process and can be done using
the graph in Figure␣ 2a.
In Figure 2a, operating frequency is plotted versus timing
capacitor (C
T
) with the upper and lower lines correspond-
ing to the minimum and maximum lock frequency given a
specific C
T
value. To choose the right timing capacitor,
find the intersection of the desired operating frequency
and the dashed line. Then move to the corresponding C
T
value.
Alternately, use the following equations as a starting point:
for f
LOCK
≥ 2MHz:
C
f
T
LOCK
=






075
250 10
40 10
6
12
.
•
–•
–
–
for f
LOCK
≤ 2MHz:
C
f
T
LOCK
=






075
310 10
60 10
6
12
.
•
–•
–
–
Figure 2a. C
T
vs Operating Frequency
Because the lock range for the PLL is nearly 2:1, the
nearest standard value NP0 capacitor can be used. For
the application shown in Figure 1, a 1.6MHz switching
frequency corresponds to an 100pF timing capacitor.
Since the switching frequency affects inductor ripple
current, the inductor must also be scaled. Table 1 shows
recommended component values for various switching
frequencies.
Table 1. Recommended Component Values for Various Switching
Frequencies (R
LP
= 3.01k)
SWITCHING
FREQUENCY C
T
C
C
C
LP
R
C
L1
600kHz 330pF 1500pF 2700pF 10k 10µH
1MHz 180pF 1000pF 2200pF 10k 6.2µH
1.6MHz 100pF 820pF 1500pF 15k 5.6µH
2MHz 68pF 820pF 1500pF 15k 4.7µH
2.5MHz 47pF 330pF 1500pF 20k 3.3µH
3MHz 33pF 330pF 1000pF 20k 2.7µH
C
T
VALUE (pF)
FREQUENCY (Hz)
10M
1310 F02a
10k
100k
10
100k
1M
1k
100
10k
MINIMUM
LOCK
FREQUECY
MAXIMUM
LOCK
FREQUECY
OPERATIO
U
V
IN
SHDNSHUTDOWN
SYNC IN
SYNC
PLL-LPF
R
LP
V
IN
5V
R
C
178k
20.5k
C
T
1310 F02a
C2
4.7µF
CERAMIC
C1
4.7µF
CERAMIC
V
OUT
12V
C
LP
C
C
FB
C
T
V
C
SW
LT1310
L1
GND
Figure 2b. Circuit Used for C
T
Selection